From patchwork Mon Dec 18 07:35:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 180177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp1083008dyi; Sun, 17 Dec 2023 23:36:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQ9PAdROLInlvQR1Us7djHXDJE1Uyad1ePk2omus4+WeWEgiYb9suIIbK5LHpk79OuuUfp X-Received: by 2002:a0c:ff46:0:b0:67e:f411:2254 with SMTP id y6-20020a0cff46000000b0067ef4112254mr6989652qvt.6.1702884988898; Sun, 17 Dec 2023 23:36:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702884988; cv=pass; d=google.com; s=arc-20160816; b=SuZXEtoQNWDIFYUvs2zjmtKM5ngdxminG3kYrUDw8UVjPTm5SvEB3+yoxP7JJN4BWk 9x5R+rDz5mgUl1l7tuHUqYdA2zAn3IIKY1W9uDYmV3kqh2yQ/26QcykfRW+h2VSMZ+eW N/R8ZKLmfXD2/O0Bmujz/uaXOiKrcQ5Hxg5iyQpK03/DiRBbiybkGSgd4na/hssaTbPu IVDeCPJHOf0JrGolwi8Zn5shuoAHg4X52G47u6HSVfRlph3Ek/1eoSBcXXhJk3OlXl+b VmJZacg/gZz3St0Jh3rrvhEvzvSVvX/NFljbEp4NCZ3kNAUHUfMyyCEXXpmviZgG/LF6 SObA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=OrHsooTdBOIRKXxzJdVJ3QxiJFKF8sKOj5cVu9nCyf4=; fh=yqBQmCEeFYB2Wjmf8l8QkV/dOy5iKwSEx/iU/FYQjxU=; b=AiYN+aiKrIY5BMdl3R1Z8tMo9k56OK3+PSmxmOg7vZ42PrmD7NKQjoa68mdinaxNpx YzJgBevNZZBBI52YmTJghcMOg2dr5LNjpJF/GhAY24kLX4G97D1bLdtc7msynGrPcIy6 KO+A7nKKor7UjX0xDZWP9c0daPMXk0wd2Bxw8EwI/Q6DyDbNmw0A85BXyQaZPQiDYNuI PrrJldOw2ZZ8ZuKv3EVoWorthWcGXmFakBb/r/wnIY0goi2R8B0Q0KhTPkEzDZi6B9SO TmQC1qFglVWfZCPeaatLCsgQwNOqcSRHyHuD6feYmK/Ql9BBvaq6mA3RpiXEwfUbWdSu Xdow== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=El9i3P38; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u15-20020a0ce5cf000000b0067ee77fafb9si14013058qvm.416.2023.12.17.23.36.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Dec 2023 23:36:28 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=El9i3P38; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C7AF3858009 for ; Mon, 18 Dec 2023 07:36:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 3D6413858424 for ; Mon, 18 Dec 2023 07:36:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3D6413858424 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3D6413858424 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.93 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702884966; cv=none; b=AroVw89VzEYm3MHb02h63ntNTzCDS4ngFDYq90gZwXgJjGEs9ngFP3/lHKzF/1oXsm+HAbRjQJYl6cuWhuid+4ws3g/432ykvO1OorNPjrYdXYDTqcus5+SUx+ksN7ohkelRmdpQZAnvLvCQYWe8I6HB1NBievQwrdfui9oxO/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702884966; c=relaxed/simple; bh=yK/qkdeRgyXiaI3zSQy/vCiC/4h7UIkRrIW92Ze+T/I=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=AqnfmBqHaoe/73HgmtScyWDzO2LXGx7h104mo79qU/zCNplob6ZvROnp3eue+0Jk2xFmlstBF68IiAbLETYtHg+Jd0F+X04CABszc89Lbrgopi2FbF669t0gseZz3WLDQa1N0VhrivCAXGjXuG4pjTBCxiJy9nlYhBHPU60Omi4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702884963; x=1734420963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yK/qkdeRgyXiaI3zSQy/vCiC/4h7UIkRrIW92Ze+T/I=; b=El9i3P38SrR8vr25ixk1oCQ45V6CBCglhzTY1/wf21+YGI2kZ5FQ/7ag F0/aOOPOc70dxpEFdvHbYR8yCdbUi5FTTa7uyPcjwWozg/zIaeFXUFGtu a0IdRO31gYoSYgnU3alwdxVWdoEC/iD/bjKQD3LU9stde2wg2YI7RDo2n Ab25RkOJOy10OyAgLKMqzXLlLuhRu88fJ4v+1GdS+V0IFfo1nYCTezqZG IvelhPqFNFPkQgkf9IbYEm/lj/JvXbUruubzmn07rWWAFnDRICY87b16Y TSzqyEhwUikIw6UkBCgGnB3Lz4O7lcXKw3sbe4HX3VJ5qNtR6AFT9ZaH4 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="392637386" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="392637386" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2023 23:36:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="948677349" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="948677349" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga005.jf.intel.com with ESMTP; 17 Dec 2023 23:35:59 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 171BF10056A4; Mon, 18 Dec 2023 15:35:59 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Bugfix for the RVV const vector Date: Mon, 18 Dec 2023 15:35:57 +0800 Message-Id: <20231218073557.2020740-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218070433.2000339-1-pan2.li@intel.com> References: <20231218070433.2000339-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785602368527724468 X-GMAIL-MSGID: 1785604330134099939 From: Pan Li This patch would like to fix one bug of const vector for interleave. Assume we need to generate interleave const vector like below. V = {{4, -4, 3, -3, 2, -2, 1, -1,} Before this patch: vsetvl a3, zero, e64, m8, ta, ma vid.v v8 v8 = {0, 1, 2, 3, 4} li a6, -1 vmul.vx v8, v8, a6 v8 = {-0, -1, -2, -3, -4} vadd.vi v24, v8, 4 v24 = { 4, 3, 2, 1, 0} vadd.vi v8, v8, -4 v8 = {-4, -5, -6, -7, -8} li a6, 32 vsll.vx v8, v8, a6 v8 = {0, -4, 0, -5, 0, -6, 0, -7,} for e32 vor v24, v24, v8 v24 = {4, -4, 3, -5, 2, -6, 1, -7,} for e32 After this patch: vsetvli a6,zero,e64,m8,ta,ma vid.v v8 v8 = {0, 1, 2, 3, 4} li a7,-1 vmul.vx v16,v8,a7 v16 = {-0, -1, -2, -3, -4} vaddvi v16,v16,4 v16 = { 4, 3, 2, 1, 0} vaddvi v8,v8,-4 v8 = {-4, -3, -2, -1, 0} li a7,32 vsll.vx v8,v8,a7 v8 = {0, -4, 0, -3, 0, -2,} for e32 vor.vv v16,v16,v8 v8 = {4, -4, 3, -3, 2, -2,} for e32 It is not easy to add asm check stable enough for this case, as we need to check the vadd -4 target comes from the vid output, which crosses 4 instructions up to point. Thus there is no test here and will be covered by gcc.dg/vect/pr92420.c in the underlying patches. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Take step2 instead of step1 for second series. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index eade8db4cf1..d1eb7a0a9a5 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1331,7 +1331,7 @@ expand_const_vector (rtx target, rtx src) rtx tmp2 = gen_reg_rtx (new_mode); base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode); expand_vec_series (tmp2, base2, - gen_int_mode (step1, new_smode)); + gen_int_mode (step2, new_smode)); rtx shifted_tmp2 = expand_simple_binop ( new_mode, ASHIFT, tmp2, gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX,