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[8.43.85.97]) by mx.google.com with ESMTPS id ff16-20020a0562140bd000b0067a8d007eb3si7841525qvb.454.2023.12.11.04.19.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 04:19:40 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5015B385802A for ; Mon, 11 Dec 2023 12:19:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 8F8593858D37 for ; Mon, 11 Dec 2023 12:19:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F8593858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8F8593858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.204.34.130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702297157; cv=none; b=UmMEKZzTOCzzvAH/LJPaVJUwZGnyc/N3dR1N3gud5DrI1K8uQW5jRxCnKE4JMIFhpATJdOshg+mPc+cXGNosfc7Finc4z95l18YQ4UZh5SqPdPxJOsrHpTSy+mD1SES4eP/EuHpAEpRqRHQG61sJKv7Dj3ME4ePijPfUD9iNcS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702297157; c=relaxed/simple; bh=PjqzhnNocGFw7S0KGsucNVjFCiswKe9vVC6nSgQ6jp8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=bryt0RwLRbzrshZQ4DUHU9kVIhHyRA1Vp1G1aqWuENR2p6Lt8qmC6FaC2NY9cHcwLaqLRk141brpxqzoMDBqojDHE/4UXPnNYxVBf3ohiYqFtWpVBjUs+TdKTFWs9vW2VGiKObTpLrmVv+/dySmiNg09XaAf8NW3/jwkFDFh+F8= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp81t1702297150tro2gr1j Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 11 Dec 2023 20:19:09 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJnFwpbqh2dCsCqsi1lFtBUMSToM2g/PlipJUKJCHY/VHBdRcm+Az rQ201DsPe/jf0MYQ+4NkcZVqaVB/48INoH7XPQCfTbgHFU6hHpys1Tixh5QQC2xp/Qv3+RA Rs16InIwZekEpxLZE5f/OxqqrSrwuPUnB/SCzn02h21sVzqCWKlEohihH7Q9p+dOhOZ43Cc fY0mqxfSuL0wRDprtXZVCkFiY3Ac87dvTp9Qyn4KJwEn/kxaAswZX+LGEpxStDwrFPFxEXw 4cXG5tjxc3Fb1hEfeMN7E9ypTEF7J4jkdq27Xf1GB0jJLBTVI1Oa76cT84kIwIVqpeJQNB9 wzqc4RWxzqVBLBxvT0HXWLkLlgjMu1lwgdXA0ixWMVRElTFInlmgJJQdqrqR1PMQgLkzDuq dTQ1Lwc9sjE= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12194650562103271589 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [COMMITTED V2] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS Date: Mon, 11 Dec 2023 20:19:03 +0800 Message-Id: <20231211121903.1864526-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784987968006405073 X-GMAIL-MSGID: 1784987968006405073 This patch fixes an ICE on record_use during RTL_SSA initialization RISC-V backend VSETVL PASS. This is the ICE: 0x11a8603 partial_subreg_p(machine_mode, machine_mode) ../../../../gcc/gcc/rtl.h:3187 0x3b695eb rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_info&, rtl_ssa::insn_info*, rtx_obj_reference) ../../../../gcc/gcc/rtl-ssa/insns.cc:524 In record_use: if (HARD_REGISTER_NUM_P (regno) && partial_subreg_p (use->mode (), mode)) Assertion failed on partial_subreg_p which is: inline bool partial_subreg_p (machine_mode outermode, machine_mode innermode) { /* Modes involved in a subreg must be ordered. In particular, we must always know at compile time whether the subreg is paradoxical. */ poly_int64 outer_prec = GET_MODE_PRECISION (outermode); poly_int64 inner_prec = GET_MODE_PRECISION (innermode); gcc_checking_assert (ordered_p (outer_prec, inner_prec)); -----> cause ICE. return maybe_lt (outer_prec, inner_prec); } RISC-V VSETVL PASS is an advanced lazy vsetvl insertion PASS after RA (register allocation). The rootcause is that we have a pattern (reduction instruction) that includes both VLA (length-agnostic) and VLS (fixed-length) modes. (insn 168 173 170 31 (set (reg:RVVM1SI 101 v5 [311]) (unspec:RVVM1SI [ (unspec:V32BI [ (const_vector:V32BI [ (const_int 1 [0x1]) repeated x32 ]) (reg:DI 30 t5 [312]) (const_int 2 [0x2]) repeated x2 (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (unspec:RVVM1SI [ (reg:V32SI 96 v0 [orig:185 vect__96.40 ] [185]) -----> VLS mode NUNITS = 32 elements. (reg:RVVM1SI 113 v17 [439]) -----> VLA mode NUNITS = [8, 8] elements. ] UNSPEC_REDUC_XOR) (unspec:RVVM1SI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF) ] UNSPEC_REDUC)) 15948 {pred_redxorv32si} In this case, record_use is trying to check partial_subreg_p (use->mode (), mode) for RTX = (reg:V32SI 96 v0 [orig:185 vect__96.40 ] [185]). use->mode () == V32SImode, wheras mode = RVVM1SImode. Then it ICE since they are !ordered_p. Set the use mode as the biggest mode which is natural fall back mode. gcc/ChangeLog: * rtl-ssa/insns.cc (function_info::record_use): Add !ordered_p case. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: New test. --- gcc/rtl-ssa/insns.cc | 11 +++++++--- .../riscv/rvv/vsetvl/vsetvl_bug-2.c | 21 +++++++++++++++++++ 2 files changed, 29 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c diff --git a/gcc/rtl-ssa/insns.cc b/gcc/rtl-ssa/insns.cc index 2fa48e0dacd..a54168d5c5f 100644 --- a/gcc/rtl-ssa/insns.cc +++ b/gcc/rtl-ssa/insns.cc @@ -520,9 +520,14 @@ function_info::record_use (build_info &bi, insn_info *insn, // the instruction (unusually) references the same register in two // different but equal-sized modes. gcc_checking_assert (use->insn () == insn); - if (HARD_REGISTER_NUM_P (regno) - && partial_subreg_p (use->mode (), mode)) - use->set_mode (mode); + if (HARD_REGISTER_NUM_P (regno)) + { + if (!ordered_p (GET_MODE_PRECISION (use->mode ()), + GET_MODE_PRECISION (mode))) + use->set_mode (reg_raw_mode[regno]); + else if (partial_subreg_p (use->mode (), mode)) + use->set_mode (mode); + } use->record_reference (ref, false); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c new file mode 100644 index 00000000000..bbc02eab818 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */ + +int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right, + safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2, + g_97_l_439; +void g_97(int * __restrict l_437) +{ + for (; g_97_l_439; g_97_l_439 += 1) + for (char l_502 = 0; l_502 < 4; l_502++) + { + int __trans_tmp_14 = ((safe_lshift_func_int32_t_s_s_right >= 2 + || safe_lshift_func_int32_t_s_s_left) + ? 1 : safe_lshift_func_int32_t_s_s_right); + long __trans_tmp_15 = __trans_tmp_14 * safe_mul_func_uint64_t_u_u_ui2; + unsigned short __trans_tmp_16 = -__trans_tmp_15; + int __trans_tmp_7 + = (__trans_tmp_16 ^ 65535UL) - safe_sub_func_uint64_t_u_u_ui2; + *l_437 ^= (short)(__trans_tmp_7 ^ g_79_2); + } +}