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[1/4] RISC-V: Add crypto vector implied ISA info.

Message ID 20231206024524.10792-1-wangfeng@eswincomputing.com
State Unresolved
Headers
Series [1/4] RISC-V: Add crypto vector implied ISA info. |

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Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Feng Wang Dec. 6, 2023, 2:45 a.m. UTC 
  Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
---
 gcc/common/config/riscv/riscv-common.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Tsukasa OI Dec. 6, 2023, 3:33 a.m. UTC | #1 
On 2023/12/06 11:45, Feng Wang wrote:
> Due to the crypto vector entension is depend on the Vector extension,
> so the "v" info is added into implied ISA info with the corresponding
> crypto vector extension.

Hi Feng,

It's true that vector crypto extensions are based on the vector
extension but it *does not* mean that it requires full the 'V'
extension.  Vector crypto extensions also consider about embedded
processors where VLEN < 128.

Quoting the documentation:

> The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn
> and Zvks-- require a Zve64x base, or application ("V") base Vector Extension.
> 
> All of the other Vector Crypto Extensions can be built on any embedded (Zve*) or application ("V")
> base Vector Extension.

So, correct dependencies to add are like follows:

> +  {"zvbb",  "zvkb"},
> +  {"zvbc",   "zve64x"},
> +  {"zvkb",   "zve32x"},
> +  {"zvkg",   "zve32x"},
> +  {"zvkned", "zve32x"},
> +  {"zvknha", "zve32x"},
> +  {"zvknhb", "zve64x"},
> +  {"zvksed", "zve32x"},
> +  {"zvksh",  "zve32x"},

Note that 'V' indirectly depends on both 'Zve32x' and 'Zve64x' so this
would be fine to represent "or application ('V')" part quoted above.

Also, consider adding those dependencies to the Python script
gcc/config/riscv/arch-canonicalize.

Thanks,
Tsukasa




> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6c210412515..dbb42ca2f1e 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
>    {"zvksc", "zvbc"},
>    {"zvksg", "zvks"},
>    {"zvksg", "zvkg"},
> +  {"zvbb",  "zvkb"},
> +  {"zvbc",     "v"},
> +  {"zvkb",     "v"},
> +  {"zvkg",     "v"},
> +  {"zvkned",   "v"},
> +  {"zvknha",   "v"},
> +  {"zvknhb",   "v"},
> +  {"zvksed",   "v"},
> +  {"zvksh",    "v"},
>  
>    {"zfh", "zfhmin"},
>    {"zfhmin", "f"},
Feng Wang Dec. 7, 2023, 2:15 a.m. UTC | #2 
2023-12-06 11:33 Tsukasa OI <research_trasio@irq.a4lg.com> wrote:



>On 2023/12/06 11:45, Feng Wang wrote:



>> Due to the crypto vector entension is depend on the Vector extension,



>> so the "v" info is added into implied ISA info with the corresponding



>> crypto vector extension.



>



>Hi Feng,



>



>It's true that vector crypto extensions are based on the vector



>extension but it *does not* mean that it requires full the 'V'



>extension.  Vector crypto extensions also consider about embedded



>processors where VLEN < 128.



>



>Quoting the documentation:



>



>> The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn



>> and Zvks-- require a Zve64x base, or application ("V") base Vector Extension.



>> 



>> All of the other Vector Crypto Extensions can be built on any embedded (Zve*) or application ("V")



>> base Vector Extension.



>



>So, correct dependencies to add are like follows:



>



>> +  {"zvbb",  "zvkb"},



>> +  {"zvbc",   "zve64x"},



>> +  {"zvkb",   "zve32x"},



>> +  {"zvkg",   "zve32x"},



>> +  {"zvkned", "zve32x"},



>> +  {"zvknha", "zve32x"},



>> +  {"zvknhb", "zve64x"},



>> +  {"zvksed", "zve32x"},



>> +  {"zvksh",  "zve32x"},



>



>Note that 'V' indirectly depends on both 'Zve32x' and 'Zve64x' so this



>would be fine to represent "or application ('V')" part quoted above.



>



>Also, consider adding those dependencies to the Python script



>gcc/config/riscv/arch-canonicalize.



>



>Thanks,



>Tsukasa



>

I modified this part. Thank you for your correction.

>



>



>



>> 



>> gcc/ChangeLog:



>> 



>> 	* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.



>> ---



>>  gcc/common/config/riscv/riscv-common.cc | 9 +++++++++



>>  1 file changed, 9 insertions(+)



>> 



>> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc



>> index 6c210412515..dbb42ca2f1e 100644



>> --- a/gcc/common/config/riscv/riscv-common.cc



>> +++ b/gcc/common/config/riscv/riscv-common.cc



>> @@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =



>>    {"zvksc", "zvbc"},



>>    {"zvksg", "zvks"},



>>    {"zvksg", "zvkg"},



>> +  {"zvbb",  "zvkb"},



>> +  {"zvbc",     "v"},



>> +  {"zvkb",     "v"},



>> +  {"zvkg",     "v"},



>> +  {"zvkned",   "v"},



>> +  {"zvknha",   "v"},



>> +  {"zvknhb",   "v"},



>> +  {"zvksed",   "v"},



>> +  {"zvksh",    "v"},



>>  



>>    {"zfh", "zfhmin"},



>>    {"zfhmin", "f"},
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6c210412515..dbb42ca2f1e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -120,6 +120,15 @@  static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksc", "zvbc"},
   {"zvksg", "zvks"},
   {"zvksg", "zvkg"},
+  {"zvbb",  "zvkb"},
+  {"zvbc",     "v"},
+  {"zvkb",     "v"},
+  {"zvkg",     "v"},
+  {"zvkned",   "v"},
+  {"zvknha",   "v"},
+  {"zvknhb",   "v"},
+  {"zvksed",   "v"},
+  {"zvksh",    "v"},
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},