From patchwork Tue Dec 5 15:16:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 174078 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp3499938vqy; Tue, 5 Dec 2023 07:17:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8yKImtJX3yOTLT0YwbgOftD6A2Fs93htxs4gqrKIl6ZHMwlLW2UqZN/55GXYolmZm9hQM X-Received: by 2002:a05:6102:390d:b0:464:9159:ba8e with SMTP id e13-20020a056102390d00b004649159ba8emr1605338vsu.31.1701789437871; Tue, 05 Dec 2023 07:17:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701789437; cv=pass; d=google.com; s=arc-20160816; b=ZUrHaHVFuutb1gomhR0HfOpC2zZfLbxeCJlYH3UqYJM9Q5inyoR5dQvnN8gA/R+ooU kiprPGV+2+sIAkWMpRDvFpLE1w+YxXOPvlzLFnK59+bcQdSXqw760y5hcg8rSPZ7saoL i0CQqntsUj8Eyb2Bya4g5QXKGOufMROl/O+yehXhEUywof5UUcsMUrV6hADwsf/xcJAI dPDJ1rUfwZp0BnU9YJfHQksokBp+KHERu31IlyH+7mh6+5oaFcKcmpAEz1MijONbwtDk CVFb+AjKVm8qowfDHrxstR0eAJXuiq1SOWKvSsJZTth/hGxE1uH5ckWPnz84p1adjK4V n7iQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=KuAwg2NHDIH2wE22UmyJJCiIeDjqVQYBsUhxJfcGeoI=; fh=Q46rxVg9O6uUuEjwRrBYdVh/xJlZbxkx1orae54gaTk=; b=DhOSjO1k7cykv1HyLj5K2Fgrk9lrw6F/1qlUf2LS6QuwXca76ZCzzBfm8lRuDIndtK 6fUX2JD9z/JKdXwnmMXqyiIkg7/cv3/ufyaWUKVDxT78E8KJHoB3pSgBPmLGuT7kdGY7 nYFSelcAPbHsqMRB8ItbOCxvIuozX4xjRV6PvzICTQbvJgR3M8P8rFNBUA384pATiDbI VvpNHDK44djAsDGvKJWkhqyB/ij8d+XTen/D9yeYgZ3hS1I+4zH+GMN2V77GwTNbt8Sm 3wfBwH1W8bunsCg0J2rTAwaHDTNqjaOsGowcP1tIV3tb5P6i0Z1UXIa9KgFPDeiOY8+y Gk5g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=GOl4G4w5; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=vrull.eu Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id i6-20020a05610220c600b00462a719d083si802416vsr.760.2023.12.05.07.17.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 07:17:17 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=GOl4G4w5; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=vrull.eu Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9EC03386D605 for ; Tue, 5 Dec 2023 15:17:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by sourceware.org (Postfix) with ESMTPS id 522B538449F2 for ; Tue, 5 Dec 2023 15:16:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 522B538449F2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 522B538449F2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::22c ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789415; cv=none; b=Sl60u878DWxXHmH8AllquPDunLoSxgZrfslIDYb39JRcGWXlZvA9g10ZP6XO4QoE9VBPrEcEvAsEObCNTuUCEXXfCKjgx5H4KkIz1em3Bl9Bs/+BGhskS+HG97zfipMHnamscLw3se2FsjN8uZh0cpd4ScnFWpcKTFx+nA94FHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789415; c=relaxed/simple; bh=mivJSko70yxpn66r3qpgbwKmOzirilctsfLsuxsbl54=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=MfjpfaKkmJa0t0kHFtzl9UNGJvJvwnkn3KL6U/A16hVE9ex2UTE5OeG1+dNmL9tC1H3fSLzRppRORmJqkuQeECt08r+CuPVnv7V3VlsTW4uFy92AdN+uMo1aJNrTiOPmcXiFqntNAEEByJDk9PCO82O5JyycHfr+t6usk02B34Y= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2c9f751663bso36741021fa.1 for ; Tue, 05 Dec 2023 07:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1701789408; x=1702394208; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=KuAwg2NHDIH2wE22UmyJJCiIeDjqVQYBsUhxJfcGeoI=; b=GOl4G4w5hnM3ZVtMqEaicDfEzkp1GBk8n8WadIY4eXvlYvX4yZjIADsXZjNEXjxMMG ju1c2rMum1kAcKYDdk7QDO/Eh1OSZ9P2I9uQEmi1r8X1KFk16HLpCAf7crtqKJ01uoUs IWZDH1kgcLUlr3LYJydbW6p+Y/OK7NW/1ALX3uNdBVVbcbdBNAUX1uJ0Qh6pHL6ugheJ cyq9V65JpKJZhqQNM0ufedlLTCR+UxLtyusllZyUuPCaGqb4HSQRj662Aiio4v3d0COf VMOFzen38/XNQ22pF0BYTNm4aLNsxZciaC68m97o0qrBAgHI2FXFfAY9Ixq6m07BnUCD lEdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701789408; x=1702394208; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KuAwg2NHDIH2wE22UmyJJCiIeDjqVQYBsUhxJfcGeoI=; b=o4DZoHkq0JretyaV5Ov33Wjk9RZ9lZxhHFkFgJsiG4CKuuMt14FjjTCKPH+0BbYLfg 412x4ABCJWR+ruFsDpEhWSijNWBxxp00vVPUTQrkh8B652Yg3RfP1qaVPJnhz57+ZG+Z xQLpdV51Q2AOb1yy8wPfvF0pwZOfIavSeL5AkT0JJmF2BwhVMdnv81o8eva3XIlSdnjt +TnzSqb15Mx6tG1lvqnnV9rY3oC7/byaTLZdaEVb3D1oTqjkOT8222SiTIMNE/akFLaK AyihNd6k3mv2GtZjUbs1Jwt++O9qIyREEpKfK16Gcc8ncC4pmN62yyYQfLQcnk3ZozwT rARw== X-Gm-Message-State: AOJu0Yz+Z6m7DYQF0ssmI7f77ZEfDz0NGndQ7wCL46m7leAedMiZGeV/ Zz7kTqGnCno3XRzaab7aTzVdkTT5GmXyaKGicKUJLg== X-Received: by 2002:a2e:9b51:0:b0:2ca:129f:3f9c with SMTP id o17-20020a2e9b51000000b002ca129f3f9cmr451918ljj.25.1701789408359; Tue, 05 Dec 2023 07:16:48 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id d8-20020a1709061f4800b00a0435148ed7sm6971254ejk.17.2023.12.05.07.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 07:16:47 -0800 (PST) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jin Ma Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH] RISC-V: xtheadmemidx: Document inline asm issue with memory constraint Date: Tue, 5 Dec 2023 16:16:44 +0100 Message-ID: <20231205151644.3203029-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784455561187857885 X-GMAIL-MSGID: 1784455561187857885 The XTheadMemIdx support relies on the fact that memory operands that can be expressed by XTheadMemIdx instructions, will only appear as operands of such instructions. For internal instruction generation this is guaranteed by the implemenation. However, in case of inline assembly, this guarantee is not given and we cannot differentiate these two cases when printing the operand: asm volatile ("sd %1,%0" : "=m"(*tmp) : "r"(val)); asm volatile ("th.srd %1,%0" : "=m"(*tmp) : "r"(val)); If XTheadMemIdx is enabled, then the address will be printed as if an XTheadMemIdx instruction is emitted, which is obviously wrong in the first case. There might be solutions to handle this (e.g. using TARGET_MEM_CONSTRAINT or extending the mnemonics to accept the standard operands for XTheadMemIdx instructions), but let's document this behavior for now as a known issue by adding xfail tests until we have an acceptable fix. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmemidx-inline-asm-1.c: New test. Reported-by: Jin Ma Signed-off-by: Christoph Müllner --- .../riscv/xtheadmemidx-inline-asm-1.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-inline-asm-1.c diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-inline-asm-1.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-inline-asm-1.c new file mode 100644 index 00000000000..da52433feb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-inline-asm-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" } */ + +/* XTheadMemIdx support is implemented such that reg+reg addressing mode + loads/stores are preferred over standard loads/stores. + If this order changed using inline assembly, the result will be invalid + instructions. This test serves the purpose of documenting this + limitation until a solution is available. */ + +void foo (void *p, unsigned long off, unsigned long val) +{ + unsigned long *tmp = (unsigned long*)(p + off); + asm volatile ("sd %1,%0" : "=m"(*tmp) : "r"(val)); +} + +void bar (void *p, unsigned long off, unsigned long val) +{ + unsigned long *tmp = (unsigned long*)(p + off); + asm volatile ("th.srd %1,%0" : "=m"(*tmp) : "r"(val)); +} + +/* { dg-final { scan-assembler "sd\t\[a-z\]\[0-9\]+,0\\(\[a-z\]\[0-9\]+\\)" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "sd\t\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,0" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "th\.srd\t\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,0" } } */ +/* { dg-final { scan-assembler-not "th\.srd\t\[a-z\]\[0-9\]+,0\\(\[a-z\]\[0-9\]+\\)" } } */