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[8.43.85.97]) by mx.google.com with ESMTPS id mh2-20020a056214564200b0067ab3389663si6313185qvb.293.2023.12.05.02.14.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 02:14:08 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6E1513860768 for ; Tue, 5 Dec 2023 10:14:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B1C5F385734D for ; Tue, 5 Dec 2023 10:13:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B1C5F385734D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B1C5F385734D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701771216; cv=none; b=x5KNrNGF5G+qGGY0Fiwyzs1YJuh+GLEX187dMYtSglCQzdYkcg1/3hDcSuFo0WqbfOKnB6HizWqZ77me36Q7d37mo1LHisaOVYBHsi37kylHq4MyS0gCGEhFfeHQyLWX0lyDgzXOKhyR+VTkDyxvJeNFBPDPXGmNvmgFczbGQ00= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701771216; c=relaxed/simple; bh=GWAR+88DcpuYwZiS0XqbszFo5aoCa+jGtUxRWvjFxj8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Ilhjny48zBzt41qAlGNDmiF+sbzStGdtqLhuW/qra5YzcEj5v33d99MxzQfMheXrBMQBklx3hUSZvH7VcJDFen3Kn5ekFZD1yqH09Hc4hs15fus9Nh+i9mxHSeepWvLCat389jCzsWnfszEuuXjbMI1mU5TpeOwvZNHoNj/a+m0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5322139F; Tue, 5 Dec 2023 02:14:20 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6AAA3F5A1; Tue, 5 Dec 2023 02:13:33 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [pushed v2 01/25] aarch64: Generalise require_immediate_lane_index Date: Tue, 5 Dec 2023 10:12:59 +0000 Message-Id: <20231205101323.1914247-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205101323.1914247-1-richard.sandiford@arm.com> References: <20231205101323.1914247-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-22.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784436488393875746 X-GMAIL-MSGID: 1784436488393875746 require_immediate_lane_index previously hard-coded the assumption that the group size is determined by the argument immediately before the index. However, for SME, there are cases where it should be determined by an earlier argument instead. gcc/ * config/aarch64/aarch64-sve-builtins.h: (function_checker::require_immediate_lane_index): Add an argument for the index of the indexed vector argument. * config/aarch64/aarch64-sve-builtins.cc (function_checker::require_immediate_lane_index): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (ternary_bfloat_lane_base::check): Update accordingly. (ternary_qq_lane_base::check): Likewise. (binary_lane_def::check): Likewise. (binary_long_lane_def::check): Likewise. (ternary_lane_def::check): Likewise. (ternary_lane_rotate_def::check): Likewise. (ternary_long_lane_def::check): Likewise. (ternary_qq_lane_rotate_def::check): Likewise. --- .../aarch64/aarch64-sve-builtins-shapes.cc | 16 ++++++++-------- gcc/config/aarch64/aarch64-sve-builtins.cc | 18 ++++++++++++------ gcc/config/aarch64/aarch64-sve-builtins.h | 3 ++- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc index af816c4c9e7..1646afc7a0d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc @@ -941,7 +941,7 @@ struct ternary_bfloat_lane_base bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3, N); + return c.require_immediate_lane_index (3, 2, N); } }; @@ -956,7 +956,7 @@ struct ternary_qq_lane_base bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3, 4); + return c.require_immediate_lane_index (3, 0); } }; @@ -1123,7 +1123,7 @@ struct binary_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (2); + return c.require_immediate_lane_index (2, 1); } }; SHAPE (binary_lane) @@ -1162,7 +1162,7 @@ struct binary_long_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (2); + return c.require_immediate_lane_index (2, 1); } }; SHAPE (binary_long_lane) @@ -2817,7 +2817,7 @@ struct ternary_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3); + return c.require_immediate_lane_index (3, 2); } }; SHAPE (ternary_lane) @@ -2845,7 +2845,7 @@ struct ternary_lane_rotate_def : public overloaded_base<0> bool check (function_checker &c) const override { - return (c.require_immediate_lane_index (3, 2) + return (c.require_immediate_lane_index (3, 2, 2) && c.require_immediate_one_of (4, 0, 90, 180, 270)); } }; @@ -2868,7 +2868,7 @@ struct ternary_long_lane_def bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3); + return c.require_immediate_lane_index (3, 2); } }; SHAPE (ternary_long_lane) @@ -2965,7 +2965,7 @@ struct ternary_qq_lane_rotate_def : public overloaded_base<0> bool check (function_checker &c) const override { - return (c.require_immediate_lane_index (3, 4) + return (c.require_immediate_lane_index (3, 0) && c.require_immediate_one_of (4, 0, 90, 180, 270)); } }; diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index c5aaf1bef17..e6ac81f6b52 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -2440,20 +2440,26 @@ function_checker::require_immediate_enum (unsigned int rel_argno, tree type) return false; } -/* Check that argument REL_ARGNO is suitable for indexing argument - REL_ARGNO - 1, in groups of GROUP_SIZE elements. REL_ARGNO counts - from the end of the predication arguments. */ +/* The intrinsic conceptually divides vector argument REL_VEC_ARGNO into + groups of GROUP_SIZE elements. Return true if argument REL_ARGNO is + a suitable constant index for selecting one of these groups. The + selection happens within a 128-bit quadword, rather than the whole vector. + + REL_ARGNO and REL_VEC_ARGNO count from the end of the predication + arguments. */ bool function_checker::require_immediate_lane_index (unsigned int rel_argno, + unsigned int rel_vec_argno, unsigned int group_size) { unsigned int argno = m_base_arg + rel_argno; if (!argument_exists_p (argno)) return true; - /* Get the type of the previous argument. tree_argument_type wants a - 1-based number, whereas ARGNO is 0-based. */ - machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, argno)); + /* Get the type of the vector argument. tree_argument_type wants a + 1-based number, whereas VEC_ARGNO is 0-based. */ + unsigned int vec_argno = m_base_arg + rel_vec_argno; + machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, vec_argno + 1)); gcc_assert (VECTOR_MODE_P (mode)); unsigned int nlanes = 128 / (group_size * GET_MODE_UNIT_BITSIZE (mode)); return require_immediate_range (rel_argno, 0, nlanes - 1); diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h index 1ac561dab47..2ca5b208efa 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.h +++ b/gcc/config/aarch64/aarch64-sve-builtins.h @@ -463,7 +463,8 @@ public: bool require_immediate_either_or (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT); bool require_immediate_enum (unsigned int, tree); - bool require_immediate_lane_index (unsigned int, unsigned int = 1); + bool require_immediate_lane_index (unsigned int, unsigned int, + unsigned int = 1); bool require_immediate_one_of (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT, HOST_WIDE_INT, HOST_WIDE_INT); bool require_immediate_range (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT);