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[8.43.85.97]) by mx.google.com with ESMTPS id p9-20020a0cfd89000000b0067aa5ce6c2dsi8095535qvr.340.2023.12.05.02.16.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 02:16:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1670A3875447 for ; Tue, 5 Dec 2023 10:16:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7418D3861833 for ; Tue, 5 Dec 2023 10:13:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7418D3861833 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7418D3861833 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701771228; cv=none; b=siMXTDsEvE1DPMF4vPZCe0UVtXPa1tA36ce5L/KeiGOE26wekGxEL7MUdJP2+uVUbB9jxQrviLIcKTHaDGs1zq48sALxaEpC2U8AWybLfaWpMbSrs7hpD+4HNNpNxTZpg6LiWnzzEgOnPmhZK/2qEv+9XazycJi86fRh6WBzVvM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701771228; c=relaxed/simple; bh=gGVRolUZmE/KmYlxk2Z386jjZhEqdqM1LUDzIQR3MCU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=wsthRtKIdCO6BL3bZIZlE+ApSBpjGPr/ojlFKvmSgOnxzb3STaUBptHiwwJReKC9vbP7n46w0UWKG/hRmwJ8Hbe+9dBczU5s2MLSHu0qtEHfktizJlD3O7XFEjl8yVGBSONrq00PRokjz5JLsL16cpHvqSTg3/1hpyGyruy8jJM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F11011477; Tue, 5 Dec 2023 02:14:31 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E2A2A3F5A1; Tue, 5 Dec 2023 02:13:44 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [pushed v2 17/25] aarch64: Add a register class for w12-w15 Date: Tue, 5 Dec 2023 10:13:15 +0000 Message-Id: <20231205101323.1914247-18-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205101323.1914247-1-richard.sandiford@arm.com> References: <20231205101323.1914247-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-22.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784436654936277549 X-GMAIL-MSGID: 1784436654936277549 Some SME instructions use w12-w15 to index ZA. This patch adds a register class for that range. gcc/ * config/aarch64/aarch64.h (W12_W15_REGNUM_P): New macro. (W12_W15_REGS): New register class. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it. * config/aarch64/aarch64.cc (aarch64_regno_regclass) (aarch64_class_max_nregs, aarch64_register_move_cost): Handle W12_W15_REGS. --- gcc/config/aarch64/aarch64.cc | 12 +++++++----- gcc/config/aarch64/aarch64.h | 6 ++++++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 5d06c7fb411..9a97b71fedc 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -11959,6 +11959,9 @@ aarch64_label_mentioned_p (rtx x) enum reg_class aarch64_regno_regclass (unsigned regno) { + if (W12_W15_REGNUM_P (regno)) + return W12_W15_REGS; + if (STUB_REGNUM_P (regno)) return STUB_REGS; @@ -12323,6 +12326,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode) unsigned int nregs, vec_flags; switch (regclass) { + case W12_W15_REGS: case STUB_REGS: case TAILCALL_ADDR_REGS: case POINTER_REGS: @@ -14693,13 +14697,11 @@ aarch64_register_move_cost (machine_mode mode, const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params.regmove_cost; - /* Caller save and pointer regs are equivalent to GENERAL_REGS. */ - if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS - || to == STUB_REGS) + /* Trest any subset of POINTER_REGS as though it were GENERAL_REGS. */ + if (reg_class_subset_p (to, POINTER_REGS)) to = GENERAL_REGS; - if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS - || from == STUB_REGS) + if (reg_class_subset_p (from, POINTER_REGS)) from = GENERAL_REGS; /* Make RDFFR very expensive. In particular, if we know that the FFR diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2d39b843d9c..57012a7c763 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -663,6 +663,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; && (REGNO) != R17_REGNUM \ && (REGNO) != R30_REGNUM) \ +#define W12_W15_REGNUM_P(REGNO) \ + IN_RANGE (REGNO, R12_REGNUM, R15_REGNUM) + #define FP_REGNUM_P(REGNO) \ (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) @@ -689,6 +692,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; enum reg_class { NO_REGS, + W12_W15_REGS, TAILCALL_ADDR_REGS, STUB_REGS, GENERAL_REGS, @@ -713,6 +717,7 @@ enum reg_class #define REG_CLASS_NAMES \ { \ "NO_REGS", \ + "W12_W15_REGS", \ "TAILCALL_ADDR_REGS", \ "STUB_REGS", \ "GENERAL_REGS", \ @@ -734,6 +739,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0x0000f000, 0x00000000, 0x00000000 }, /* W12_W15_REGS */ \ { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \