[committed] RISC-V: Add sifive-x280 to -mcpu
Checks
Commit Message
x280 is one of SiFive core, and it release for a while, also
upstream LLVM already support that.
[1] https://www.sifive.com/cores/intelligence-x280
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add sifive-x280.
* doc/invoke.texi (RISC-V Options): Add sifive-x280
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-sifive-x280.c: New test.
---
gcc/config/riscv/riscv-cores.def | 1 +
gcc/doc/invoke.texi | 2 +-
.../gcc.target/riscv/mcpu-sifive-x280.c | 20 +++++++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-x280.c
@@ -73,6 +73,7 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
+RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series")
RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
@@ -29776,7 +29776,7 @@ by particular CPU name.
Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
@samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
@samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
-@samp{sifive-u54}, and @samp{sifive-u74}.
+@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}.
@opindex mtune
@item -mtune=@var{processor-string}
new file mode 100644
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */
+/* SiFive x280 => rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_c) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zvfh) \
+ && defined(__riscv_zvl512b) \
+ && defined(__riscv_v))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}