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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id x2-20020ac87ec2000000b0042385d3d064si2840951qtj.521.2023.12.01.02.12.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 02:12:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eCqLCj6p; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EC653385AE43 for ; Fri, 1 Dec 2023 10:12:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id F09903858C20 for ; Fri, 1 Dec 2023 10:12:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F09903858C20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F09903858C20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.136 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701425526; cv=none; b=lX9rHpBPaLoZIP8kQci8JGwQR7V0bBnZNHgiXgp02WYUOmET1XobE+BC+lEMm0VB/newLK9ZAcQUBmbj6D1am8nNaiL4vQqdNWg2ZAFjWGjz/8uD7ulPxQHiNcBGsBXJiQefcM7zcxix5hSzDnZyVxVK8T9rYvuP7Y24wxFZF7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701425526; c=relaxed/simple; bh=4Q10Uo7res+nmSw7MLdESqDTV5zbESyPYVq/J09Nfrk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=E8Q6qPfIot8+xNi+nzgLb5/eTzDOePJyBlTxVqvACjpfFAO9nXKAVraePIjnpFsfddbfh59vHEC+BJwWKQ9D3BgjwWu128sm0BDqf0FpN0dfZO+w7xocX/dQ36Cm/Uq3BsIJyzKqnIDy4AWl9o0kuHy54sYNUo10wMIclq4VC6U= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701425525; x=1732961525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4Q10Uo7res+nmSw7MLdESqDTV5zbESyPYVq/J09Nfrk=; b=eCqLCj6puTbZmI02ucbnhLhJR1Sj3+Ev3DDopNeDXtrwhPhH3XEwXdZY A6ezKsLSS1V9sha/IwFyoDBhLfRKpGSrT02Gi/Zr57i63Tj37kelON5JX Cb2VUBLm0x8uR3lWRvOb+nIBL9nCsxBOk673HEhuUqfPoDZEKIY8wESyO Lbn2yzJRIG1ZUEHnQaWCMBQoC7doaNjTvXGhG0sV1Q2TeKCWTRcryfjeB Ef5+0/mk+TFalBserNB92CL1Anowx5E1CJZIEGPrZyvC8LI+Zct4dmfps Fpz5oNRg0xZZiKh4TZX7wOGKHf/XTXuku43cnxKM1nalmQW2dNHqbO1t8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="372862228" X-IronPort-AV: E=Sophos;i="6.04,241,1695711600"; d="scan'208";a="372862228" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2023 02:12:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="913537693" X-IronPort-AV: E=Sophos;i="6.04,241,1695711600"; d="scan'208";a="913537693" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 01 Dec 2023 02:12:00 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 133A2100571A; Fri, 1 Dec 2023 18:12:00 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v3] RISC-V: Bugfix for legitimize move when get vec mode in zve32f Date: Fri, 1 Dec 2023 18:11:58 +0800 Message-Id: <20231201101158.2774595-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130072105.2462309-1-pan2.li@intel.com> References: <20231130072105.2462309-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783972650873595611 X-GMAIL-MSGID: 1784073999909024918 From: Pan Li If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. However, this approach doesn't honor DFmode when movdf pattern when ZVE32f and of course results in ICE when zve32f. This patch would like to reuse the approach with some additional handing, consider lowpart bits is meaningless for FP mode, we need one int reg as bridge here. For example: rtx tmp = gen_rtx_reg (DImode) reg:DI = reg:DF (fmv.d.x) // Move DF reg to DI ... perform the extract for high and low parts ... reg:DF = reg:DI (fmv.x.d) // Move DI reg back to DF after all done PR target/112743 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Take the exist (U *mode) and handle DFmode like DImode when EEW is 32bits for ZVE32F. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-2.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 63 +++++++++++++------ .../gcc.target/riscv/rvv/base/pr112743-2.c | 52 +++++++++++++++ 2 files changed, 95 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a4fc858fb50..2fbaaf01078 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2605,41 +2605,64 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) unsigned int nunits = vmode_size > mode_size ? vmode_size / mode_size : 1; scalar_mode smode = as_a (mode); unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size; - unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1; + unsigned int num = (smode == DImode || smode == DFmode) + && !TARGET_VECTOR_ELEN_64 ? 2 : 1; + bool need_int_reg_p = false; if (num == 2) { /* If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. */ + need_int_reg_p = smode == DFmode; smode = SImode; nunits = nunits * 2; } - vmode = riscv_vector::get_vector_mode (smode, nunits).require (); - rtx v = gen_lowpart (vmode, SUBREG_REG (src)); - for (unsigned int i = 0; i < num; i++) + if (riscv_vector::get_vector_mode (smode, nunits).exists (&vmode)) { - rtx result; - if (num == 1) - result = dest; - else if (i == 0) - result = gen_lowpart (smode, dest); - else - result = gen_reg_rtx (smode); - riscv_vector::emit_vec_extract (result, v, index + i); + rtx v = gen_lowpart (vmode, SUBREG_REG (src)); + rtx int_reg = dest; - if (i == 1) + if (need_int_reg_p) { - rtx tmp - = expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result), - gen_int_mode (32, Pmode), NULL_RTX, 0, - OPTAB_DIRECT); - rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0, - OPTAB_DIRECT); - emit_move_insn (dest, tmp2); + int_reg = gen_reg_rtx (DImode); + emit_move_insn (int_reg, gen_lowpart (GET_MODE (int_reg), dest)); } + + for (unsigned int i = 0; i < num; i++) + { + rtx result; + if (num == 1) + result = int_reg; + else if (i == 0) + result = gen_lowpart (smode, int_reg); + else + result = gen_reg_rtx (smode); + + riscv_vector::emit_vec_extract (result, v, index + i); + + if (i == 1) + { + rtx tmp = expand_binop (Pmode, ashl_optab, + gen_lowpart (Pmode, result), + gen_int_mode (32, Pmode), NULL_RTX, 0, + OPTAB_DIRECT); + rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, int_reg, + NULL_RTX, 0, + OPTAB_DIRECT); + emit_move_insn (int_reg, tmp2); + } + } + + if (need_int_reg_p) + emit_move_insn (dest, gen_lowpart (GET_MODE (dest), int_reg)); + else + emit_move_insn (dest, int_reg); } + else + gcc_unreachable (); + return true; } /* Expand diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c new file mode 100644 index 00000000000..fdb35fd70f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c @@ -0,0 +1,52 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +#include + +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) + +#define P 53 +#define Exp_shift 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) + +double ulp (double _x) +{ + union double_union x, a; + register int L; + + x.d = _x; + L = (word0 (x) & Exp_mask) - (P - 1) * Exp_msk1; + + if (L > 0) + { + L |= Exp_msk1 >> 4; + word0 (a) = L; + word1 (a) = 0; + } + else + { + L = -L >> Exp_shift; + if (L < Exp_shift) + { + word0 (a) = 0x80000 >> L; + word1 (a) = 0; + } + else + { + word0 (a) = 0; + L -= Exp_shift; + word1 (a) = L >= 31 ? 1 : 1 << (31 - L); + } + } + + return a.d; +}