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[8.43.85.97]) by mx.google.com with ESMTPS id pt15-20020a056214048f00b0067a395ef2d3si71439qvb.70.2023.11.28.22.37.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 22:37:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y7fCQkLO; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 40DBE385C40C for ; Wed, 29 Nov 2023 06:37:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 92A473858CDA for ; Wed, 29 Nov 2023 06:37:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 92A473858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 92A473858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.120 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701239829; cv=none; b=DLAh2WLyZy8t5md9MMmcZxEQgbZiY7uRTDhB14reBITw4QsS1zpC+szhUpwpJoXXVTZ9XOqUSXD8C41430fJctxzPdvZzA5+AFkKYcCHlIvKbRicobAgsIx7TNjbvyZTZi6ULzCv622DHH1AjU4QJl2ZddwwqZqPideD09q97Gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701239829; c=relaxed/simple; bh=k8mC5/Pa89bsbHFBEyCi50rKf6BoSggYkfFa4de67xc=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Sc27PhPvozP00d28nRtvIUo/0Q3pJKYf0HYqDsbVtFtu9uDIjqS3p2M3awjmGUF3/C7csQoJAQBf9VKGodJhybVzqttS/4o9y+qFo3gsbD91KoqW033X6DIZ0ybVqgSylv8u94H74GV+3d+rdrxO0CBxuWhgIqLbXTJh8EWxUU4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701239827; x=1732775827; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=k8mC5/Pa89bsbHFBEyCi50rKf6BoSggYkfFa4de67xc=; b=Y7fCQkLOJCGxkuwmrXSRFuev9tHuIP/WA6LXtpQm5jPZiEMgVYLFGS7R 6o9mUMikaWnOTRqJjDH6Hiyc19XndqtXSCOpcx6w9VXswEP+IlgkZrrv9 StAoRd+3zkE68FGZi2CTFSYDmcMf2W94MPjAYTyneqJ2CZcbf4xnVsG3c PaQ7iJrltfQGkPkFrk0pp2MgcW0kbmBlY0xidkg9qfPAIObE9F7FMGoWM 7b8yc7V8VTDGNFDdRC7oWqtH0Rf9CgOyjiWcNZwHudCMeXUb5KU4404pb RMIm/wCe2zkPPFx+ggJvjC3Tq3jjhsPmas8lynM82wsm06dvkU8hqphNo Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="391974109" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="391974109" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 22:37:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="16914410" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa001.jf.intel.com with ESMTP; 28 Nov 2023 22:37:04 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id DDF4F1005629; Wed, 29 Nov 2023 14:37:02 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for ICE in block move when zve32f Date: Wed, 29 Nov 2023 14:37:01 +0800 Message-Id: <20231129063701.1988235-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783879279228890894 X-GMAIL-MSGID: 1783879279228890894 From: Pan Li The exact_div requires the exactly multiple of the divider. Unfortunately, the condition will be broken when zve32f in some cases. For example, potential_ew is 8 BYTES_PER_RISCV_VECTOR * lmul1 is [4, 4] This patch would like to ensure the precondition of exact_div when get_vec_mode. PR 112743 gcc/ChangeLog: * config/riscv/riscv-string.cc (expand_block_move): Add precondition check for exact_div. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-0.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-string.cc | 1 + .../gcc.target/riscv/rvv/base/pr112743-0.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 3b5e05e2c44..80e3b5981af 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -866,6 +866,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in) if (TARGET_MIN_VLEN * lmul <= nunits * BITS_PER_UNIT /* Avoid loosing the option of using vsetivli . */ && (nunits <= 31 * lmul || nunits > 31 * 8) + && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, potential_ew) && (riscv_vector::get_vector_mode (elem_mode, exact_div (BYTES_PER_RISCV_VECTOR * lmul, potential_ew)).exists (&vmode))) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c new file mode 100644 index 00000000000..2e62e60d89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-0.c @@ -0,0 +1,16 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +typedef struct test_a { + void *x; + char a[10]; + short b[2]; + int c[1]; +} test_type_t; + +void +test_copy_memory (test_type_t *out, test_type_t *in) +{ + *out = *in; +}