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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id t3-20020a05620a034300b0076d1c784892si10445879qkm.478.2023.11.28.02.12.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 02:12:14 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8282A3847736 for ; Tue, 28 Nov 2023 10:12:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by sourceware.org (Postfix) with ESMTP id 53BFE385800B for ; Tue, 28 Nov 2023 10:11:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 53BFE385800B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 53BFE385800B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=206.189.21.223 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701166308; cv=none; b=KULFsM4lMhNXFnV3fp9Cj5jEkz3REQhgF+EdhNSpylR85AInPegtURBa+LdutmeH79xCDwOvxf2zNCrQuN8Yd1KM7aL+cBJbaDUvfeep3IvGlnFmVA3dMotUym1zC7aX1NqtLE239askRpYKz8qoUPrPtvwa/cmMvXt9OLr13Vw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701166308; c=relaxed/simple; bh=NoyK7CExxJcAh2AHtxVdnIUtNO4h6oiPXEiLjioPoh8=; h=From:To:Subject:Date:Message-Id; b=L9Lwsyjf2TZ0AjObGHAeRhKIyS/+Y8B4RHfoOzTSRwasrR0UUCEorLJlphCvxs47LNNArMeHOtMDNawS1czUtdz25jdpDXCB24DWlJ9i2dia3oinYiYRl5IkzpBe21y4R6fOn4x+pJuKuNOmpqPgczhnJf8uUCb51sz2Hd5nYlg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgBXMn+lvGVlraoBAA--.11537S4; Tue, 28 Nov 2023 18:10:46 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH] [ifcvt][V2] optimize x=c ? (y and z) : y, where z is a reg or imm Date: Tue, 28 Nov 2023 10:10:47 +0000 Message-Id: <20231128101047.12989-1-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgBXMn+lvGVlraoBAA--.11537S4 X-Coremail-Antispam: 1UD129KBjvJXoW3Ar47Cw4ruryxXr4ktF1xGrg_yoWfJrWkpF W3W34UCrs5JFyrJF48WFy3J3Z0934Yqw1UCrn3JrWfuwsIvrZ5Kr4Fkw1avr17JFZ3ZF12 ka98AFsFgry7J37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkI14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783802190014463925 X-GMAIL-MSGID: 1783802190014463925 Take the following case for example. CFLAGS: -march=rv64gc_zbb_zicond -mabi=lp64d -O2 long test_AND_ceqz (long x, long y, long z, long c) { if (c) x = y & z; else x = y; return x; } Before patch: and a2,a1,a2 czero.eqz a0,a2,a3 czero.nez a3,a1,a3 or a0,a3,a0 ret After patch: and a0,a1,a2 czero.nez a1,a1,a3 or a0,a1,a0 ret Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for AND. (noce_bbs_ok_for_cond_zero_arith): Likewise. (noce_try_cond_zero_arith): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for AND. --- gcc/ifcvt.cc | 86 +++-- .../gcc.target/riscv/zicond_ifcvt_opt.c | 323 +++++++++++++++++- 2 files changed, 377 insertions(+), 32 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 4cc6a125ff0..a1af762b5aa 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2940,7 +2940,7 @@ noce_cond_zero_binary_op_supported (rtx op) opcode = GET_CODE (XEXP (op, 0)); if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR - || noce_cond_zero_shift_op_supported (opcode)) + || opcode == AND || noce_cond_zero_shift_op_supported (opcode)) return true; return false; @@ -3021,7 +3021,7 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, { common = b; bin_op1 = XEXP (bin_exp, 1); - czero_code = reverse + czero_code = (reverse ^ (GET_CODE (bin_exp) == AND)) ? noce_reversed_cond_code (if_info) : GET_CODE (cond); } @@ -3053,7 +3053,7 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, static int noce_try_cond_zero_arith (struct noce_if_info *if_info) { - rtx target, a; + rtx target, rtmp, a; rtx_insn *seq; machine_mode mode = GET_MODE (if_info->x); rtx common = NULL_RTX; @@ -3073,44 +3073,70 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) bin_code = GET_CODE (bin_exp); bin_op0 = XEXP (bin_exp, 0); - if (CONST_INT_P (*to_replace)) + if (bin_code == AND) { - non_zero_op = gen_reg_rtx (mode); - noce_emit_move_insn (non_zero_op, *to_replace); + rtmp = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (rtmp, a)); + + target = noce_emit_czero (if_info, czero_code, common, if_info->x); + if (!target) + { + end_sequence (); + return false; + } + + target = expand_simple_binop (mode, IOR, rtmp, target, if_info->x, 0, + OPTAB_WIDEN); + if (!target) + { + end_sequence (); + return false; + } + + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); } else - non_zero_op = *to_replace; + { + if (CONST_INT_P (*to_replace)) + { + non_zero_op = gen_reg_rtx (mode); + noce_emit_move_insn (non_zero_op, *to_replace); + } + else + non_zero_op = *to_replace; - /* If x is used in both input and out like x = c ? x + z : x, - use a new reg to avoid modifying x */ - if (common && rtx_equal_p (common, if_info->x)) - target = gen_reg_rtx (mode); - else - target = if_info->x; + /* If x is used in both input and out like x = c ? x + z : x, + use a new reg to avoid modifying x */ + if (common && rtx_equal_p (common, if_info->x)) + target = gen_reg_rtx (mode); + else + target = if_info->x; - target = noce_emit_czero (if_info, czero_code, non_zero_op, target); - if (!target || !to_replace) - { - end_sequence (); - return false; - } + target = noce_emit_czero (if_info, czero_code, non_zero_op, target); + if (!target || !to_replace) + { + end_sequence (); + return false; + } - if (CONST_INT_P (*to_replace)) - { - if (noce_cond_zero_shift_op_supported (bin_code)) + if (CONST_INT_P (*to_replace)) { - *to_replace = gen_rtx_SUBREG (E_QImode, target, 0); - if (GET_CODE (a) == ZERO_EXTEND && bin_code == LSHIFTRT) - PUT_CODE (a, SIGN_EXTEND); + if (noce_cond_zero_shift_op_supported (bin_code)) + { + *to_replace = gen_rtx_SUBREG (E_QImode, target, 0); + if (GET_CODE (a) == ZERO_EXTEND && bin_code == LSHIFTRT) + PUT_CODE (a, SIGN_EXTEND); + } + else if (SUBREG_P (bin_op0)) + *to_replace = gen_rtx_SUBREG (GET_MODE (bin_op0), target, 0); + else + *to_replace = target; } - else if (SUBREG_P (bin_op0)) - *to_replace = gen_rtx_SUBREG (GET_MODE (bin_op0), target, 0); else *to_replace = target; + emit_insn (gen_rtx_SET (if_info->x, a)); } - else - *to_replace = target; - emit_insn (gen_rtx_SET (if_info->x, a)); seq = end_ifcvt_sequence (if_info); if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index c6b0518968b..53206d76e9f 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -1349,5 +1349,324 @@ test_RotateR_eqz_imm_int (unsigned int x, unsigned int y, unsigned int c) return x; } -/* { dg-final { scan-assembler-times {czero\.eqz} 78 } } */ -/* { dg-final { scan-assembler-times {czero\.nez} 56 } } */ +long +test_AND_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y & z; + else + x = y; + return x; +} + +long +test_AND_ceqz_x (long x, long z, long c) +{ + if (c) + x = x & z; + + return x; +} + +long +test_AND_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y & z; + return x; +} + +long +test_AND_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x & z; + return x; +} + +long +test_AND_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y & z; + else + x = y; + return x; +} + +long +test_AND_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x & z; + + return x; +} + +long +test_AND_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y & z; + return x; +} + +long +test_AND_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x & z; + return x; +} + +long +test_AND_ceqz_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = z & y; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + x = z & x; + + return x; +} + +long +test_AND_nez_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = z & y; + return x; +} + +long +test_AND_nez_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + { + } + else + x = z & x; + return x; +} + +long +test_AND_nez_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = z & y; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + x = z & x; + + return x; +} + +long +test_AND_eqz_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = z & y; + return x; +} + +long +test_AND_eqz_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + { + } + else + x = z & x; + return x; +} + +long +test_AND_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y & 11; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_imm (long x, long c) +{ + if (c) + x = x & 11; + + return x; +} + +long +test_AND_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y & 11; + return x; +} + +long +test_AND_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x & 11; + return x; +} + +long +test_AND_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y & 11; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x & 11; + + return x; +} + +long +test_AND_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y & 11; + return x; +} + +long +test_AND_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x & 11; + return x; +} + +long +test_AND_ceqz_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = 11 & y; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + x = 11 & x; + + return x; +} + +long +test_AND_nez_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = y; + else + x = 11 & y; + return x; +} + +long +test_AND_nez_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + { + } + else + x = 11 & x; + return x; +} + +long +test_AND_nez_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = 11 & y; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + x = 11 & x; + + return x; +} + +long +test_AND_eqz_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = y; + else + x = 11 & y; + return x; +} + +long +test_AND_eqz_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + { + } + else + x = 11 & x; + return x; +} +/* { dg-final { scan-assembler-times {czero\.eqz} 94 } } */ +/* { dg-final { scan-assembler-times {czero\.nez} 72 } } */