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server2.sourceware.org X-QQ-mid: bizesmtp68t1700741258t6obqvvz Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 23 Nov 2023 20:07:37 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 7YFKcddXagj3D9FQSqex1inqhebPgK7kGtvzN31kImOYyyxlxopBXXO20396r 6Cj3tAiFN0z4RhhYcr0qq3/F+YtuHlwJsgclYJ8Hv++EnqoqEEEITxVFT6S6UZFIcb5gmbO rBtQ1r9D+M4TpZgxpxlpFWvKMuDqU9DL68GXnGHGRGcOM4ik5KW8UclMHgJ4qO0OzC9ivm2 YTp0uz8yE283MCeab0GqnBZ6Zw6VBszJB4EnxQncmF3iK87O2+sw6RXUQD94WPG33++2zLP Lw557h0R/SMNm5yh8xFanj5G6AGSRFwajBJc2TTEVDBm2Z9uGVo6iukmJeM3u8xe879EQ3O 7TLD6IuU4vprJH9PUsoK3G2khISFmzMefcZmgzdNarRDUhnCFDKFyEFaaSc9suKMV9ODR5C 8aepmIo/rdQ= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5514439870897839254 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Add wrapper for emit vec_extract[NFC] Date: Thu, 23 Nov 2023 20:07:35 +0800 Message-Id: <20231123120735.1632594-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783356499733076594 X-GMAIL-MSGID: 1783356499733076594 Add wrapper for vec_extract since my following patch will need to call it. gcc/ChangeLog: * config/riscv/riscv-protos.h (emit_vec_extract): New function. * config/riscv/riscv-v.cc (emit_vec_extract): Ditto. * config/riscv/riscv.cc (riscv_legitimize_move): Refine codes. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 12 +----------- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 52097fe48cf..c74c2e94a4f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -558,6 +558,7 @@ void expand_cond_binop (unsigned, rtx *); void expand_cond_ternop (unsigned, rtx *); void expand_popcount (rtx *); void expand_rawmemchr (machine_mode, rtx, rtx, rtx); +void emit_vec_extract (rtx, rtx, poly_int64); /* Rounding mode bitfield for fixed point VXRM. */ enum fixed_point_rounding_mode diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 24b09c0dd2d..72b96d8339d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4636,4 +4636,26 @@ can_be_broadcasted_p (rtx op) return can_create_pseudo_p () && nonmemory_operand (op, mode); } +/* Helper function to emit vec_extract_optab. */ +void +emit_vec_extract (rtx target, rtx src, poly_int64 index) +{ + machine_mode vmode = GET_MODE (src); + machine_mode smode = GET_MODE (target); + class expand_operand ops[3]; + enum insn_code icode + = convert_optab_handler (vec_extract_optab, vmode, smode); + gcc_assert (icode != CODE_FOR_nothing); + create_output_operand (&ops[0], target, smode); + ops[0].target = 1; + create_input_operand (&ops[1], src, vmode); + if (index.is_constant ()) + create_integer_operand (&ops[2], index); + else + create_input_operand (&ops[2], gen_int_mode (index, Pmode), Pmode); + expand_insn (icode, 3, ops); + if (ops[0].value != target) + emit_move_insn (target, ops[0].value); +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d0efb939bf2..425463ebb18 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2616,14 +2616,10 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) nunits = nunits * 2; } vmode = riscv_vector::get_vector_mode (smode, nunits).require (); - enum insn_code icode - = convert_optab_handler (vec_extract_optab, vmode, smode); - gcc_assert (icode != CODE_FOR_nothing); rtx v = gen_lowpart (vmode, SUBREG_REG (src)); for (unsigned int i = 0; i < num; i++) { - class expand_operand ops[3]; rtx result; if (num == 1) result = dest; @@ -2631,13 +2627,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) result = gen_lowpart (smode, dest); else result = gen_reg_rtx (smode); - create_output_operand (&ops[0], result, smode); - ops[0].target = 1; - create_input_operand (&ops[1], v, vmode); - create_integer_operand (&ops[2], index + i); - expand_insn (icode, 3, ops); - if (ops[0].value != result) - emit_move_insn (result, ops[0].value); + riscv_vector::emit_vec_extract (result, v, index + i); if (i == 1) {