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[8.43.85.97]) by mx.google.com with ESMTPS id k10-20020ac85fca000000b0041e4be2d3c7si938330qta.360.2023.11.23.02.55.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 02:55:45 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65AA83858431 for ; Thu, 23 Nov 2023 10:55:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id C6E513858D33 for ; Thu, 23 Nov 2023 10:55:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C6E513858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C6E513858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=13.245.218.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700736919; cv=none; b=bfRFKOaLgOg/+EZCIgIPf2kC+d8kAo62NLrD6Vs6xeuR9pzQH9UYcfgnU2HQKoOxVgrXZtTv1BUYlUJ5A6Nyo3aKzMuk+ASlJ+riF+Vg7DVYI4ZruAyygmOxwX35y5GKEXUo/ctoHAMZhKXOONf5lTXAWnXtBBnK3PnVGSxFLeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700736919; c=relaxed/simple; bh=Mmv3/AgRCZcFWxXtFmq9K1Nr7qUXQB0OUoWUuohdQg8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=TkhxtHyaRvjAOvwG+Rr6I8hGAOTspDAUAAQ3i9qF06Dqgj3CmoH67+29oqHFXr9dZmAxio7JjVGVIuIQhmdgxt9MiikwLViBIa2afiYYpTqPpTrwMosGF6jNmKNtsreMVERld851Ne8K8RGlIeIQ+J6zEG0P0V9BDOIUuy9GwZY= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp88t1700736905tof9pzg6 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 23 Nov 2023 18:55:04 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 90EFqYDyPxDvh4aUGWfKsRKjN01q793hDIEPF5VSF/+Mr7sPv5tgojj7j+mk7 bbeqVju9pq3wwd/0fiV5o29SlQB5lyAWtSiWt8NyDbXx6PShnc75WLJYBmpncQ+G0tyu/Vz mCONcXFexeOynZmjUkvv5NF96tlxgzrHpSh05V35gX08P6M3xub6cn0GWmFjhF1XNh14zPv fNPeY02rwcveKqxrPAhBHKOJLJ+enTfSr/81mAF1M1J0rnIqzZcoO6n0WE6qABGePxcQsZP cG2gffZCqbYwEREXqi2eTybUbQYavjSMo1Nywwe9jsXPNpPaajCIqGRbfCwGel/rsncqygs 2fjGYsEDySKKaGLk8qRIGBDILBN+Q1lIiy+ID3HQIC0FCAofC4zhhgpXX4QgYSzNQqXqFIt +phT9vaerNBAoq+0695r/g== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2819128901800547484 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Refine some codes of riscv-v.cc[NFC] Date: Thu, 23 Nov 2023 18:55:03 +0800 Message-Id: <20231123105503.3913200-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783351943504910165 X-GMAIL-MSGID: 1783351943504910165 This patch is NFC patch to refine unreasonable codes I notice. Tested on zvl128b/zvl256b/zvl512b/zvl1024b no regression. Committed. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Refine codes. (emit_vlmax_masked_gather_mu_insn): Ditto. (modulo_sel_indices): Ditto. (expand_vec_perm): Ditto. (shuffle_generic_patterns): Ditto. --- gcc/config/riscv/riscv-v.cc | 54 +++++++++++++------------------------ 1 file changed, 18 insertions(+), 36 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 7d3e8038dab..24b09c0dd2d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -294,8 +294,6 @@ public: "vsetvl zero, rs1/imm". */ poly_uint64 nunits = GET_MODE_NUNITS (vtype_mode); len = gen_int_mode (nunits, Pmode); - if (!satisfies_constraint_K (len)) - len = force_reg (Pmode, len); vls_p = true; } else if (can_create_pseudo_p ()) @@ -846,24 +844,6 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel) } else if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode))) icode = code_for_pred_gatherei16 (data_mode); - else if (CONST_VECTOR_P (sel) - && GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)) > 16 - && riscv_get_v_regno_alignment (data_mode) > 1) - { - /* If the inner mode of data is not QI or HI and data_lmul > 1, - emitting vrgatherei16.vv instruction will lower register - pressure. - data_mode sel_mode ei16 - RVVM1QI RVVM1QI RVVM2HI not needed - RVVM2QI RVVM2QI RVVM4HI not needed - RVVM2HI RVVM2HI RVVM2HI not needed - RVVM2SI RVVM2SI RVVM1HI need - RVVM4SI RVVM4SI RVVM2HI need - RVVM8DI RVVM8DI RVVM2HI need */ - PUT_MODE (sel, get_vector_mode (HImode, - GET_MODE_NUNITS (data_mode)).require ()); - icode = code_for_pred_gatherei16 (data_mode); - } else icode = code_for_pred_gather (data_mode); rtx ops[] = {target, op, sel}; @@ -877,13 +857,13 @@ emit_vlmax_masked_gather_mu_insn (rtx target, rtx op, rtx sel, rtx mask) insn_code icode; machine_mode data_mode = GET_MODE (target); machine_mode sel_mode = GET_MODE (sel); - if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode))) - icode = code_for_pred_gatherei16 (data_mode); - else if (const_vec_duplicate_p (sel, &elt)) + if (const_vec_duplicate_p (sel, &elt)) { icode = code_for_pred_gather_scalar (data_mode); sel = elt; } + else if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode))) + icode = code_for_pred_gatherei16 (data_mode); else icode = code_for_pred_gather (data_mode); rtx ops[] = {target, mask, target, op, sel}; @@ -2703,15 +2683,21 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, return false; } -/* Modulo all SEL indices to ensure they are all in range if [0, MAX_SEL]. */ +/* Modulo all SEL indices to ensure they are all in range if [0, MAX_SEL]. + MAX_SEL is nunits - 1 if rtx_equal_p (op0, op1). Otherwise, it is + 2 * nunits - 1. */ static rtx -modulo_sel_indices (rtx sel, poly_uint64 max_sel) +modulo_sel_indices (rtx op0, rtx op1, rtx sel) { rtx sel_mod; machine_mode sel_mode = GET_MODE (sel); poly_uint64 nunits = GET_MODE_NUNITS (sel_mode); - /* If SEL is variable-length CONST_VECTOR, we don't need to modulo it. */ - if (!nunits.is_constant () && CONST_VECTOR_P (sel)) + poly_uint64 max_sel = rtx_equal_p (op0, op1) ? nunits - 1 : 2 * nunits - 1; + /* If SEL is variable-length CONST_VECTOR, we don't need to modulo it. + Or if SEL is constant-length within [0, MAX_SEL], no need to modulo the + indice. */ + if (CONST_VECTOR_P (sel) + && (!nunits.is_constant () || const_vec_all_in_range_p (sel, 0, max_sel))) sel_mod = sel; else { @@ -2761,9 +2747,7 @@ expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) out-of-range indices, so we need to modulo all the vec_perm indices to ensure they are all in range of [0, nunits - 1] when op0 == op1 or all in range of [0, 2 * nunits - 1] when op0 != op1. */ - rtx sel_mod - = modulo_sel_indices (sel, - rtx_equal_p (op0, op1) ? nunits - 1 : 2 * nunits - 1); + rtx sel_mod = modulo_sel_indices (op0, op1, sel); /* Check if the two values vectors are the same. */ if (rtx_equal_p (op0, op1)) @@ -2772,15 +2756,13 @@ expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) return; } - rtx max_sel = gen_const_vector_dup (sel_mode, 2 * nunits - 1); - /* This following sequence is handling the case that: __builtin_shufflevector (vec1, vec2, index...), the index can be any value in range of [0, 2 * nunits - 1]. */ machine_mode mask_mode; mask_mode = get_mask_mode (data_mode); rtx mask = gen_reg_rtx (mask_mode); - max_sel = gen_const_vector_dup (sel_mode, nunits); + rtx max_sel = gen_const_vector_dup (sel_mode, nunits); /* Step 1: generate a mask that should select everything >= nunits into the * mask. */ @@ -3282,15 +3264,15 @@ shuffle_generic_patterns (struct expand_vec_perm_d *d) return false; } } + else if (riscv_get_v_regno_alignment (sel_mode) > 1 + && GET_MODE_INNER (sel_mode) != HImode) + sel_mode = get_vector_mode (HImode, nunits).require (); /* Success! */ if (d->testing_p) return true; rtx sel = vec_perm_indices_to_rtx (sel_mode, d->perm); - /* 'mov' generte interleave vector. */ - if (!nunits.is_constant ()) - sel = force_reg (sel_mode, sel); /* Some FIXED-VLMAX/VLS vector permutation situations call targethook instead of expand vec_perm, we handle it directly. */ expand_vec_perm (d->target, d->op0, d->op1, sel);