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[8.43.85.97]) by mx.google.com with ESMTPS id z3-20020a0cd783000000b00653589bac4fsi8919170qvi.48.2023.11.21.02.04.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:04:57 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 12CD03857B92 for ; Tue, 21 Nov 2023 10:04:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 102653858289 for ; Tue, 21 Nov 2023 10:02:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 102653858289 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 102653858289 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700560942; cv=none; b=AKgmCPGp3dT0cMrPG2WASkZOhnlikxw1e77nMedF94k9tTWzybe+9zhw++5VYhRcpua3oRyw+rpTGThmcx6YxxHGJzK+qjRXZ0c9rtKVyym2TcpZfpvUsLigzPkZcH+SgJZsR+NFIQaN+/r83E2MSt4DMsLihslTwtwRpolSNUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700560942; c=relaxed/simple; bh=qXw9cJoWb5YDTYbKBzuS1F2OchMa3N9ItwVGNneukiU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=MsPiYhRk+YWr7b3CFFpC+9/SGUlopEYFijsDQfrsyUGKS3QEm2vKg0O8twg09W7HbhERxQhoIpCRwX5loCG/TN3G5Y5kpuDfdCLA+yF0JXLu+VwFxLWOiBGcdZmkTCIGn/ZT2aisBQVjDuoTVDu/5AyAf6/AgM5fzsKwyCJjIDI= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp76t1700560932tqq7fqh0 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 21 Nov 2023 18:02:10 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: W+onFc5Tw4PiPH7vSjm5wa6yK9FYhlOpDcmUPgTdlt75fetPnZs47dCqc5Cwc U/DsrN8i13/Z5prnixdpmd4a5xWX5ZxsHjpacWGJ01EDbzBGJDszKVB6CFwFDuEYcnMBSs5 lPwKKNdoWDydsQwVuxQjnaqnQ6jzk5lsLfb367AXVY5pFcjwE+zBbemuWv1hEMoDDjklIzx 2roo4z321OSgRvEIyqI0mS4v8AByJJECK7FcWo2UKg/+Q8DkDzCZfgGYWoXfnZyq64qqurh VDOt9NcRydFRORZXqkrieP1L0x14vxPcdzN/oe9s4JkcpWubWIfHsaqNaqFUIQ4VVy9O586 MIxVS22taHTZadPY9jBRCU/OlYRrT4AE2nlusNh66AF2gq+lmiuAx5LUpIvTNa3lpLkJrcx Gvukco5Bo+TOpjcadmfsvw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2567869848249087389 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [BUG FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32 Date: Tue, 21 Nov 2023 18:02:09 +0800 Message-Id: <20231121100209.315304-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783167553727848509 X-GMAIL-MSGID: 1783167553727848509 This bug is exposed when testing on zvl512b RV32 system. The rootcause is RA reload DI CONST_VECTOR into vmv.v.x then it ICE. So disallow DI CONST_VECTOR on RV32. PR target/112598 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Disallow DI CONST_VECTOR on RV32. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112598-1.c: New test. --- gcc/config/riscv/riscv.cc | 8 +++ .../gcc.target/riscv/rvv/autovec/pr112598-1.c | 56 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3701f41b1b3..60d3f617395 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1598,6 +1598,14 @@ riscv_const_insns (rtx x) rtx elt; if (const_vec_duplicate_p (x, &elt)) { + /* We don't allow CONST_VECTOR for DI vector on RV32 + system since the ELT constant value can not held + within a single register to disable reload a DI + register vec_duplicate into vmv.v.x. */ + scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); + if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) + && !immediate_operand (elt, Pmode)) + return 0; /* Constants from -16 to 15 can be loaded with vmv.v.i. The Wc0, Wc1 constraints are already covered by the vi constraint so we do not need to check them here diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c new file mode 100644 index 00000000000..a1d7e5bf17b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -O3 -fno-vect-cost-model -ffast-math" } */ + +#include +#define TEST_UNARY_CALL_CVT(TYPE_IN, TYPE_OUT, CALL) \ + void test_##TYPE_IN##_##TYPE_OUT##_##CALL ( \ + TYPE_OUT *out, TYPE_IN *in, unsigned count) \ + { \ + for (unsigned i = 0; i < count; i++) \ + out[i] = CALL (in[i]); \ + } +#define TEST_ASSERT(TYPE) \ + void test_##TYPE##_assert (TYPE *out, TYPE *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + if (out[i] != ref[i]) \ + __builtin_abort (); \ + } \ + } +#define TEST_INIT_CVT(TYPE_IN, VAL_IN, TYPE_REF, VAL_REF, NUM) \ + void test_##TYPE_IN##_##TYPE_REF##_init_##NUM ( \ + TYPE_IN *in, TYPE_REF *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + in[i] = VAL_IN; \ + ref[i] = VAL_REF; \ + } \ + } +#define RUN_TEST_CVT(TYPE_IN, TYPE_OUT, NUM, CALL, IN, OUT, REF, SIZE) \ + test_##TYPE_IN##_##TYPE_OUT##_init_##NUM (IN, REF, SIZE); \ + test_##TYPE_IN##_##TYPE_OUT##_##CALL (OUT, IN, SIZE); \ + test_##TYPE_OUT##_assert (OUT, REF, SIZE); + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +int64_t out[ARRAY_SIZE]; +int64_t ref[ARRAY_SIZE]; + +TEST_UNARY_CALL_CVT (float, int64_t, __builtin_llceilf) + +TEST_ASSERT (int64_t) + + +TEST_INIT_CVT (float, 9223372036854775808.0, int64_t, 0x7fffffffffffffff, 26) +TEST_INIT_CVT (float, __builtin_inf (), int64_t, __builtin_llceilf (__builtin_inf ()), 29) + +int64_t +main () +{ + RUN_TEST_CVT (float, int64_t, 26, __builtin_llceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int64_t, 29, __builtin_llceilf, in, out, ref, ARRAY_SIZE); + return 0; +}