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[8.43.85.97]) by mx.google.com with ESMTPS id 8-20020ac85748000000b004180ac7c98bsi7491583qtx.20.2023.11.20.05.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:11:50 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A70D4385B51E for ; Mon, 20 Nov 2023 13:11:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id E24D13858D39 for ; Mon, 20 Nov 2023 13:11:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E24D13858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E24D13858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.207.19.206 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700485888; cv=none; b=jmxF6AmQBu9J6Im3FxEPbbTRY0jnfFan0IEYK6UHkqoxZf/soOKzJUDK/tTHS0bDcRU6+TVn13PDqmh3eBSI1W/jZK66DwIl+yV5aFJj1UF+LC3sq5bdZR+IN5hpolL/kgrlreBQuCkFSunKdSdCubQp0iZQZqy/gdL3q8sNLD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700485888; c=relaxed/simple; bh=AUfIFxxcgmKQ32osXQJHQB2mRKU7Xcsp9o/ySBRQf7w=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=nr5tD+Vw0Eo5OoPF53h7Fs9c66DOarcF6+7Ye7esq3nanAUkuFaFAgG9zwWIR3g6NtSMmfyild9A/5fgzKbqYiolvrxucaqs9RQr27/S3WmfWqNtR5C5RBuMLvOAvyR3pDNc2XmJ4mRWucElft4IND2JIi9dLSmUE6Mn2ZlWvn8= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp77t1700485876tpp5gjpi Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 20 Nov 2023 21:11:15 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfmhi4cMXEyTdF2WTiBH+6WzcdE0u9k112F6MBZF+ygoYpN1iJdQT uZqxziAR19HhSBn/KtLj3R4MCN3qZcbDGz41N2xFm9oKK4RQ5msY74y/FWwGubMTFg0KHEE wmdUa+GWEYE7DZsX/MgySUEhUIIpZqOc3a1/hlT2XzaGVCQnOKXUU/U/0JhkddfFN9L6vUG oS0H+9ugytSIUZ+Jjbm/knbXUcxLQO9Nv3h84Pv02AmFgmw5jna+hqDbsiDsmC2fxbAcWyb oawOp7Wn+Ka9Uar+TKtv6LotPTvfHPUO+EqqI9XmOwokegRzsudRh/Zk43FRJGWs3gWm+wr TOZi7pm1LHEf5uPAY/KyEh+yLN83UJ1tV/IHdmh6SId2+QaM+OvhaWXpsOe7TMSZchIFZeK 0HbtmzizEK1nF2Ips5TYUqUBf5jd2bYd X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3256709365155791843 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [BUG FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 Date: Mon, 20 Nov 2023 21:11:14 +0800 Message-Id: <20231120131114.2801087-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783088714347644630 X-GMAIL-MSGID: 1783088714347644630 This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax ICE: bug.c:10:1: error: unrecognizable insn: 10 | } | ^ (insn 10 9 11 2 (set (reg:V4SI 140) (unspec:V4SI [ (unspec:V4BI [ (const_vector:V4BI [ (const_int 1 [0x1]) repeated x4 ]) (const_int 4 [0x4]) (const_int 2 [0x2]) repeated x3 (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (unspec:V4SI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF) (subreg:V4SI (reg:V2DI 138 [ v ]) 0) (subreg:SI (reg/v:DI 136 [ b ]) 0) ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1 (nil)) The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI which is totally same as V4SI on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax. The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use get_vector_mode to get right mode. PR target/112597 gcc/ChangeLog: * config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE. * config/riscv/vector.md: Fix slide1 intermediate mode bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112597-1.c: New test. --- gcc/config/riscv/vector-iterators.md | 28 ------------------- gcc/config/riscv/vector.md | 5 +++- .../gcc.target/riscv/rvv/autovec/pr112597-1.c | 13 +++++++++ 3 files changed, 17 insertions(+), 29 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 859f7bd1cdc..8c047e4c5e2 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3198,34 +3198,6 @@ (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") ]) -(define_mode_attr VDEMOTE [ - (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RVVM1SI") - (V1DI "V2SI") - (V2DI "V4SI") - (V4DI "V8SI") - (V8DI "V16SI") - (V16DI "V32SI") - (V32DI "V64SI") - (V64DI "V128SI") - (V128DI "V256SI") - (V256DI "V512SI") - (V512DI "V1024SI") -]) - -(define_mode_attr VMDEMOTE [ - (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI "RVVMF32BI") - (V1DI "V2BI") - (V2DI "V4BI") - (V4DI "V8BI") - (V8DI "V16BI") - (V16DI "V32BI") - (V32DI "V64BI") - (V64DI "V128BI") - (V128DI "V256BI") - (V256DI "V512BI") - (V512DI "V1024BI") -]) - (define_mode_attr stride_predicate [ (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand") (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d1499d330ff..4aed25e54f1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8096,8 +8096,11 @@ (match_operand: 4 "reg_or_int_operand")] VSLIDES1))] "TARGET_VECTOR" { + poly_uint64 nunits = GET_MODE_NUNITS (mode) * 2; + machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require (); + machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require (); if (riscv_vector::slide1_sew64_helper (, mode, - mode, mode, + vsimode, vbimode, operands)) DONE; }) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c new file mode 100644 index 00000000000..73aa3ee2f51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */ + +#include + +typedef int64_t vnx2di __attribute__ ((vector_size (16))); + +__attribute__ ((noipa)) void +f_vnx2di (int64_t a, int64_t b, int64_t *out) +{ + vnx2di v = {a, b}; + *(vnx2di *) out = v; +}