diff mbox series

[Committed,V2] RISC-V: Optimize constant AVL for LRA pattern

Message ID 20231119140803.4168318-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [Committed,V2] RISC-V: Optimize constant AVL for LRA pattern |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Nov. 19, 2023, 2:08 p.m. UTC 
  This optimization was discovered in the tuple move splitted bug fix patch.

Before this patch:

vsetivli        zero,4,e16,mf2,ta,ma
        lhu     a3,96(a5)
        vlseg8e16.v     v1,(a5)
        lw      a4,%lo(e)(a2)
        vsetvli a6,zero,e64,m2,ta,ma
        addi    a0,a7,8
        vse16.v v1,0(a7)
        vse16.v v2,0(a0)
        addi    a0,a0,8
        vse16.v v3,0(a0)
        addi    a0,a0,8
        vse16.v v4,0(a0)
        addi    a0,a0,8
        vse16.v v5,0(a0)
        addi    a0,a0,8
        vse16.v v6,0(a0)
        addi    a0,a0,8
        vse16.v v7,0(a0)
        addi    a0,a0,8
        vse16.v v8,0(a0)

After this patch:

vsetivli	zero,4,e64,m2,ta,ma
	addi	a0,a7,8
	vlseg8e16.v	v1,(a5)
	vse16.v	v1,0(a7)
	vse16.v	v2,0(a0)
	addi	a0,a0,8
	vse16.v	v3,0(a0)
	addi	a0,a0,8
	vse16.v	v4,0(a0)
	addi	a0,a0,8
	vse16.v	v5,0(a0)
	addi	a0,a0,8
	vse16.v	v6,0(a0)
	addi	a0,a0,8
	vse16.v	v7,0(a0)
	addi	a0,a0,8
	vse16.v	v8,0(a0)

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/post-ra-avl.c: New test.

---
 gcc/config/riscv/riscv-v.cc                   | 20 ++++++++++++++++---
 .../riscv/rvv/autovec/post-ra-avl.c           | 16 +++++++++++++++
 2 files changed, 33 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index f769c1474e0..594cc4dd145 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -374,10 +374,24 @@  void
 emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
 {
   gcc_assert (!can_create_pseudo_p ());
+  machine_mode mode = GET_MODE (ops[0]);
 
-  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
-  e.set_vl (vl);
-  e.emit_insn ((enum insn_code) icode, ops);
+  if (imm_avl_p (mode))
+    {
+      /* Even though VL is a real hardreg already allocated since
+	 it is post-RA now, we still gain benefits that we emit
+	 vsetivli zero, imm instead of vsetvli VL, zero which is
+	 we can be more flexible in post-RA instruction scheduling.  */
+      insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
+      e.set_vl (gen_int_mode (GET_MODE_NUNITS (mode), Pmode));
+      e.emit_insn ((enum insn_code) icode, ops);
+    }
+  else
+    {
+      insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
+      e.set_vl (vl);
+      e.emit_insn ((enum insn_code) icode, ops);
+    }
 }
 
 /* Emit an RVV insn with a predefined vector length.  Contrary to
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
new file mode 100644
index 00000000000..f3d12bac7cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+int a, b, c, e;
+short d[7][7] = {};
+int foo() {
+  short f;
+  c = 0;
+  for (; c <= 6; c++) {
+    e |= d[c][c] & 1;
+    b &= f & 3;
+  }
+  return a;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero} 1 } } */