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server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r4FJI-0000cb-Bv for gcc-patches@gcc.gnu.org; Sat, 18 Nov 2023 02:00:11 -0500 Received: from loongson.cn (unknown [10.20.4.191]) by gateway (Coremail) with SMTP id _____8DxVujqYFhlROs6AA--.15698S3; Sat, 18 Nov 2023 14:59:55 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.191]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxE+TbYFhl9BZGAA--.24585S4; Sat, 18 Nov 2023 14:59:53 +0800 (CST) From: Guo Jie To: gcc-patches@gcc.gnu.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, i@xen0n.name, xry111@xry111.site, Guo Jie Subject: [PATCH] LoongArch: Optimize the loading of immediate numbers with the same high and low 32-bit values Date: Sat, 18 Nov 2023 14:59:16 +0800 Message-Id: <20231118065916.14855-1-guojie@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxE+TbYFhl9BZGAA--.24585S4 X-CM-SenderInfo: xjxryx3h6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBj93XoWxAF1ruw1xuF1kCFWfArWfXrc_yoW5uF4Dpa y2vrn5tr48XF93KF18J3s8Grs3Jrs3Gw4agasIqryxur47J3sIgF18G39rXF1UJa1UXry2 g3Wxua4Yga15X3cCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkjb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AK xVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64 vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8G jcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2I x0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK 8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UE-erUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=guojie@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782884169139272131 X-GMAIL-MSGID: 1782884169139272131 For the following immediate load operation in gcc/testsuite/gcc.target/loongarch/imm-load1.c: long long r = 0x0101010101010101; Before this patch: lu12i.w $r15,16842752>>12 ori $r15,$r15,257 lu32i.d $r15,0x1010100000000>>32 lu52i.d $r15,$r15,0x100000000000000>>52 After this patch: lu12i.w $r15,16842752>>12 ori $r15,$r15,257 bstrins.d $r15,$r15,63,32 gcc/ChangeLog: * config/loongarch/loongarch.cc (enum loongarch_load_imm_method): Add new method. (loongarch_build_integer): Add relevant implementations for new method. (loongarch_move_integer): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/imm-load1.c: Change old check. --- gcc/config/loongarch/loongarch.cc | 22 ++++++++++++++++++- .../gcc.target/loongarch/imm-load1.c | 3 ++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index d05743bec87..58c00344d09 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -142,12 +142,16 @@ struct loongarch_address_info METHOD_LU52I: Load 52-63 bit of the immediate number. + + METHOD_MIRROR: + Copy 0-31 bit of the immediate number to 32-63bit. */ enum loongarch_load_imm_method { METHOD_NORMAL, METHOD_LU32I, - METHOD_LU52I + METHOD_LU52I, + METHOD_MIRROR }; struct loongarch_integer_op @@ -1556,11 +1560,23 @@ loongarch_build_integer (struct loongarch_integer_op *codes, int sign31 = (value & (HOST_WIDE_INT_1U << 31)) >> 31; int sign51 = (value & (HOST_WIDE_INT_1U << 51)) >> 51; + + unsigned HOST_WIDE_INT hival = value >> 32; + unsigned HOST_WIDE_INT loval = value << 32 >> 32; + /* Determine whether the upper 32 bits are sign-extended from the lower 32 bits. If it is, the instructions to load the high order can be ommitted. */ if (lu32i[sign31] && lu52i[sign31]) return cost; + /* If the lower 32 bits are the same as the upper 32 bits, just copy + the lower 32 bits to the upper 32 bits. */ + else if (loval == hival) + { + codes[cost].method = METHOD_MIRROR; + codes[cost].curr_value = value; + return cost + 1; + } /* Determine whether bits 32-51 are sign-extended from the lower 32 bits. If so, directly load 52-63 bits. */ else if (lu32i[sign31]) @@ -3230,6 +3246,10 @@ loongarch_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) gen_rtx_AND (DImode, x, GEN_INT (0xfffffffffffff)), GEN_INT (codes[i].value)); break; + case METHOD_MIRROR: + gcc_assert (mode == DImode); + emit_insn (gen_insvdi (x, GEN_INT (32), GEN_INT (32), x)); + break; default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load1.c b/gcc/testsuite/gcc.target/loongarch/imm-load1.c index 2ff02971239..f64cc2956a3 100644 --- a/gcc/testsuite/gcc.target/loongarch/imm-load1.c +++ b/gcc/testsuite/gcc.target/loongarch/imm-load1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mabi=lp64d -O2" } */ -/* { dg-final { scan-assembler "test:.*lu52i\.d.*\n\taddi\.w.*\n\.L2:" } } */ +/* { dg-final { scan-assembler-not "test:.*lu52i\.d.*\n\taddi\.w.*\n\.L2:" } } */ +/* { dg-final { scan-assembler "test:.*lu12i\.w.*\n\tbstrins\.d.*\n\.L2:" } } */ extern long long b[10];