diff mbox series

[v2,5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa

Message ID 20231117204323.453536-6-xry111@xry111.site
State Unresolved
Headers
Series Add LoongArch v1.1 div32 and ld-seq-sa support |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Xi Ruoyao Nov. 17, 2023, 8:43 p.m. UTC 
  This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other".  Thus
we can omit the "load-load" barrier dbar 0x700.

This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
	print dbar 0x700 if TARGET_LD_SEQ_SA.
	* config/loongarch/sync.md (atomic_load<mode>): Likewise.
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/sync.md      | 9 +++++----
 2 files changed, 6 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index b4bb2b6eeb5..5d3282c5e93 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6057,7 +6057,7 @@  loongarch_print_operand (FILE *file, rtx op, int letter)
       if (loongarch_cas_failure_memorder_needs_acquire (
 	    memmodel_from_int (INTVAL (op))))
 	fputs ("dbar\t0b10100", file);
-      else
+      else if (!TARGET_LD_SEQ_SA)
 	fputs ("dbar\t0x700", file);
       break;
 
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 67848d72b87..ce3ce89a61d 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -119,13 +119,14 @@  (define_insn "atomic_load<mode>"
     case MEMMODEL_SEQ_CST:
       return "dbar\t0x11\\n\\t"
 	     "ld.<size>\t%0,%1\\n\\t"
-	     "dbar\t0x14\\n\\t";
+	     "dbar\t0x14";
     case MEMMODEL_ACQUIRE:
       return "ld.<size>\t%0,%1\\n\\t"
-	     "dbar\t0x14\\n\\t";
+	     "dbar\t0x14";
     case MEMMODEL_RELAXED:
-      return "ld.<size>\t%0,%1\\n\\t"
-	     "dbar\t0x700\\n\\t";
+      return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
+			      : "ld.<size>\t%0,%1\\n\\t"
+				"dbar\t0x700";
 
     default:
       /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,