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[8.43.85.97]) by mx.google.com with ESMTPS id ee1-20020a05620a800100b0077c0f390197si1042189qkb.226.2023.11.16.05.22.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 05:22:05 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b=QRjyIOJi; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5D90B3860750 for ; Thu, 16 Nov 2023 13:21:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 95BC4385840E for ; Thu, 16 Nov 2023 13:19:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 95BC4385840E Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 95BC4385840E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700140766; cv=none; b=h0wApcCtuBkmyUyTfsqb8a5FjuTxmhbbDYW3ILsEFS3nWwCK5QV7e6cqNt6I05Mkl3DudN3T+O0d4LRq6f+hrZ/HWCB7GU2650uBS7Z2RzGFWPYGIRRsrrTD9oiDrR+NdfAr+5LvdLU+etVkVz+Ob9udbU2CJiMJsciWN4V1XqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700140766; c=relaxed/simple; bh=NAvG5XP2Fz3CgKd9JqGIMSFZVGueF629/YG1lnwf3iw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Aw2QZCiS44NSXTHo/7CDNnSavvZiEF/ZEJ0RkanJgh2+urlbYBrEMItUmYPOh074Ty5hIYXlr66ZVPeaFCCKaCed22XWA8JpQnHAi5oeTnieo96NTv8qe8ic2sdQsB1YgemjQ8jodGDMrSU9i31Cq+flUh4fcNrEniQxPweVK6w= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700140762; bh=NAvG5XP2Fz3CgKd9JqGIMSFZVGueF629/YG1lnwf3iw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QRjyIOJi6m12NZgxJSJ4vXdKBeQBph6GFfIquXuchX62TlUiCFOssJ1RWg9hbZwq3 Q6kQxrtc9MMRzCG58kz7ucbXteD+pYF+Y4Zf1khlP92Swpj0WHnsllkxAN/Hykdr9n fHU3REmXIvkruYKgDjb2mBQiv8UxQQr++v1RrHAA= Received: from stargazer.. (unknown [113.200.174.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0E3A966C0B; Thu, 16 Nov 2023 08:19:20 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH 5/5] LoongArch: Add -march=la664 and -mtune=la664 Date: Thu, 16 Nov 2023 21:18:37 +0800 Message-ID: <20231116131836.504699-7-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231116131836.504699-2-xry111@xry111.site> References: <20231116131836.504699-2-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782726971258361360 X-GMAIL-MSGID: 1782726971258361360 Allow using -march=la664 and -mtune=la664. -march=la664 implies -mdiv32 and -mld-seq-sa. -mtune=la664 is currently same as -mtune=la464 and it may need an update later. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Add la664 as STR_CPU_LA664. * config/loongarch/genopts/loongarch.opt.in (cpu_type): Add la664. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch-def.h (CPU_LA664): Define. (N_ARCH_TYPES): Increase to 5. (N_TUNE_TYPES): Increase to 5. * config/loongarch/loongarch-def.cc (loongarch_cpu_strings): Set [CPU_LA664] to STR_CPU_LA664. (loongarch_cpu_default_isa): Set [CPU_LA664] to {ISA_BASE_LA64V100, ISA_EXT_FPU64, ISA_EXT_SIMD_LASX} with OPTION_MASK_ISA_DIV32 and OPTION_MASK_ISA_LD_SEQ_SA implied. (loongarch_cpu_cache): Set [CPU_LA664] to la464_cache (). The CPUCFG fields about cache are same on LA464 and LA664. (loongarch_cpu_align): Set [CPU_LA664] to la464_align (). This may be inaccurate and need an update. (loongarch_cpu_issue_rate): Set [CPU_LA664] to 4. This may be inaccurate and need an update. (loongarch_cpu_multipass_dfa_lookahead): Set [CPU_LA664] to 4. This may be inaccurate and need an update. * config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Return true for -mtune=la664 for now. --- .../loongarch/genopts/loongarch-strings | 1 + gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++ gcc/config/loongarch/loongarch-def.cc | 26 ++++++++++++++----- gcc/config/loongarch/loongarch-def.h | 5 ++-- gcc/config/loongarch/loongarch-opts.h | 6 +++-- gcc/config/loongarch/loongarch-str.h | 1 + gcc/config/loongarch/loongarch.opt | 3 +++ 7 files changed, 35 insertions(+), 10 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index 8e412f7536e..7bc4824007e 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -26,6 +26,7 @@ STR_CPU_NATIVE native STR_CPU_ABI_DEFAULT abi-default STR_CPU_LOONGARCH64 loongarch64 STR_CPU_LA464 la464 +STR_CPU_LA664 la664 # Base architecture STR_ISA_BASE_LA64V100 la64 diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 4a22039681f..483b185b059 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64) EnumValue Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464) +EnumValue +Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664) + m@@OPTSTR_ARCH@@= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET) -m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA. diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc index 9c2ec1ec135..cf8b66e9130 100644 --- a/gcc/config/loongarch/loongarch-def.cc +++ b/gcc/config/loongarch/loongarch-def.cc @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see #define IN_TARGET_CODE #include "config.h" #include "system.h" +#include "coretypes.h" +#include "options.h" #include "loongarch-def.h" #include "loongarch-str.h" @@ -38,7 +40,8 @@ array_tune loongarch_cpu_strings = array_tune () .set (CPU_NATIVE, STR_CPU_NATIVE) .set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT) .set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64) - .set (CPU_LA464, STR_CPU_LA464); + .set (CPU_LA464, STR_CPU_LA464) + .set (CPU_LA664, STR_CPU_LA664); array_arch loongarch_cpu_default_isa = array_arch () @@ -50,7 +53,14 @@ array_arch loongarch_cpu_default_isa = loongarch_isa () .base_ (ISA_BASE_LA64V100) .fpu_ (ISA_EXT_FPU64) - .simd_ (ISA_EXT_SIMD_LASX)); + .simd_ (ISA_EXT_SIMD_LASX)) + .set (CPU_LA664, + loongarch_isa () + .base_ (ISA_BASE_LA64V100) + .fpu_ (ISA_EXT_FPU64) + .simd_ (ISA_EXT_SIMD_LASX) + .evol_add_feat (OPTION_MASK_ISA_DIV32) + .evol_add_feat (OPTION_MASK_ISA_LD_SEQ_SA)); static inline loongarch_cache la464_cache () { @@ -64,7 +74,8 @@ static inline loongarch_cache la464_cache () array_tune loongarch_cpu_cache = array_tune () .set (CPU_LOONGARCH64, la464_cache ()) - .set (CPU_LA464, la464_cache ()); + .set (CPU_LA464, la464_cache ()) + .set (CPU_LA664, la464_cache ()); /* not changed */ static inline loongarch_align la464_align () { @@ -74,7 +85,8 @@ static inline loongarch_align la464_align () array_tune loongarch_cpu_align = array_tune () .set (CPU_LOONGARCH64, la464_align ()) - .set (CPU_LA464, la464_align ()); + .set (CPU_LA464, la464_align ()) + .set (CPU_LA664, la464_align ()); #define COSTS_N_INSNS(N) ((N) * 4) @@ -115,12 +127,14 @@ const loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size = array_tune loongarch_cpu_issue_rate = array_tune () .set (CPU_NATIVE, 4) .set (CPU_LOONGARCH64, 4) - .set (CPU_LA464, 4); + .set (CPU_LA464, 4) + .set (CPU_LA664, 4); array_tune loongarch_cpu_multipass_dfa_lookahead = array_tune () .set (CPU_NATIVE, 4) .set (CPU_LOONGARCH64, 4) - .set (CPU_LA464, 4); + .set (CPU_LA464, 4) + .set (CPU_LA664, 4); /* Wiring string definitions from loongarch-str.h to global arrays with standard index values from loongarch-opts.h, so we can diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index e74036fda33..87a66d9ce30 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -156,8 +156,9 @@ struct loongarch_target #define CPU_ABI_DEFAULT 1 #define CPU_LOONGARCH64 2 #define CPU_LA464 3 -#define N_ARCH_TYPES 4 -#define N_TUNE_TYPES 4 +#define CPU_LA664 4 +#define N_ARCH_TYPES 5 +#define N_TUNE_TYPES 5 /* parallel tables. */ extern loongarch_def_array diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index aa99e510282..9badecb7cb6 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -89,8 +89,10 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, #define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX) -/* TARGET_ macros for use in *.md template conditionals */ -#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) +/* TARGET_ macros for use in *.md template conditionals. + For now treat LA664 in the same way as LA464. */ +#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464 || \ + la_target.cpu_tune == CPU_LA664) /* Note: optimize_size may vary across functions, while -m[no]-memcpy imposes a global constraint. */ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 3fa2ed5fc49..d9f4cc53d4c 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_ABI_DEFAULT "abi-default" #define STR_CPU_LOONGARCH64 "loongarch64" #define STR_CPU_LA464 "la464" +#define STR_CPU_LA664 "la664" #define STR_ISA_BASE_LA64V100 "la64" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index b17df1302f7..a8be307f92d 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -115,6 +115,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64) EnumValue Enum(cpu_type) String(la464) Value(CPU_LA464) +EnumValue +Enum(cpu_type) String(la664) Value(CPU_LA664) + march= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET) -march=PROCESSOR Generate code for the given PROCESSOR ISA.