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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id q14-20020a19430e000000b004fe951827easm1861417lfa.196.2023.11.15.22.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 22:15:54 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov , Philipp Tomsich Subject: [PATCH] aarch64: costs: update for TARGET_CSSC Date: Thu, 16 Nov 2023 07:15:51 +0100 Message-Id: <20231116061551.1218932-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782700188274892510 X-GMAIL-MSGID: 1782700188274892510 With the addition of CSSC (Common Short Sequence Compression) instructions, a number of idioms match to single instructions (e.g., abs) that previously expanded to multi-instruction sequences. This recognizes (some of) those idioms that are now misclassified and returns a cost of a single instruction. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_rtx_costs): Support idioms matching to CSSC instructions, if target CSSC is present Signed-off-by: Philipp Tomsich --- gcc/config/aarch64/aarch64.cc | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 800a8b0e110..d89c94519e9 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -14431,10 +14431,17 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED, return false; case CTZ: - *cost = COSTS_N_INSNS (2); + if (!TARGET_CSSC) + { + /* Will be split to a bit-reversal + clz */ + *cost = COSTS_N_INSNS (2); + + if (speed) + *cost += extra_cost->alu.clz + extra_cost->alu.rev; + } + else + *cost = COSTS_N_INSNS (1); - if (speed) - *cost += extra_cost->alu.clz + extra_cost->alu.rev; return false; case COMPARE: @@ -15373,12 +15380,17 @@ cost_plus: } else { - /* Integer ABS will either be split to - two arithmetic instructions, or will be an ABS - (scalar), which we don't model. */ - *cost = COSTS_N_INSNS (2); - if (speed) - *cost += 2 * extra_cost->alu.arith; + if (!TARGET_CSSC) + { + /* Integer ABS will either be split to + two arithmetic instructions, or will be an ABS + (scalar), which we don't model. */ + *cost = COSTS_N_INSNS (2); + if (speed) + *cost += 2 * extra_cost->alu.arith; + } + else + *cost = COSTS_N_INSNS (1); } return false; @@ -15388,13 +15400,15 @@ cost_plus: { if (VECTOR_MODE_P (mode)) *cost += extra_cost->vect.alu; - else + else if (GET_MODE_CLASS (mode) == MODE_FLOAT) { /* FMAXNM/FMINNM/FMAX/FMIN. TODO: This may not be accurate for all implementations, but we do not model this in the cost tables. */ *cost += extra_cost->fp[mode == DFmode].addsub; } + else if (TARGET_CSSC) + *cost = COSTS_N_INSNS (1); } return false;