From patchwork Wed Nov 15 09:47:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 165240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2429642vqg; Wed, 15 Nov 2023 01:50:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IEHkGikpdJ4pogY/YNwrOajxLZnmUbigOM+iWWvncvhhkocq9UCP3rXqpae8UtdxCbNMxRd X-Received: by 2002:a05:6214:21ea:b0:670:85e1:3902 with SMTP id p10-20020a05621421ea00b0067085e13902mr6026036qvj.57.1700041831747; Wed, 15 Nov 2023 01:50:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700041831; cv=pass; d=google.com; s=arc-20160816; b=b9cpMWc30Qc0iyWHPWbAqSC9EySdLNAySieUrywtqaPDJFgFvtP+Se3Xz+qDnDpcvA ctw3rn1KtYsFEePC4xOTrKFybgycs8jo8g4Pkx0Y8jES07d/a11MV8QOvwT00pPOOPjW QU6HtjqQOyBPUBDiw1mndYsV306AJy3ItMQef1K8+lhp1dnKyaNbFRidFngT7AkfmPh+ abRGc7iOdN0WAd8cxC3J8RvjgkBCHVm4lqJdzRdKyFo2gO7L5o0MQ6I1mwklYbJF8A+G BaeysqUDzs97hO5NBwduxEV1SXJM3/pHDXfg09VxpBKx9NzCxPcdDlLxYam8ssFPR5jL 2MwQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=+xIKs1WKZyydd2L/Ur942H5HaVL0dsdNTQL65SufBcc=; fh=n8eNxIWSYJwy/CU3QSXzDvE/zeEoomCGojuOcYEQEyQ=; b=m3qUgiDJ5m9+rVe63o5zwsH5K5TrhkzRURzJ5KsnMiPrQg1DjOZK5T8Iz2gKdgk48F sL8PxHe+mlt9mSWoMZU12mn1jlJ6LoN6Gw3tjTdhf0PZmCPsbflGmq04NpXmr0SiJKFl PX5mWiC5e8tqJDbdnM4/pnrIsXyss7qNBPXC81SQpeblEJa7hDbIQSVoSumL1drp4wM+ SE+Tqeo69rUMJufLxJzZALkluHmcjIJmGM53W6ZRb5ydlPMub5Z3WCfXWzIq0uLJ2p59 q9/Y9dBGuGrqYMHwQ88ElbXy3nIeBRfoiGxyKmZhppiKm6ar39IE9LLlcslcR0V4ELGH PQ2w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=akEtIAAh; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id k11-20020a0cc78b000000b0066d0543b654si8844905qvj.341.2023.11.15.01.50.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 01:50:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=akEtIAAh; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 846763857BA6 for ; Wed, 15 Nov 2023 09:50:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id DF7413857C56 for ; Wed, 15 Nov 2023 09:47:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF7413857C56 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DF7413857C56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.100 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041640; cv=none; b=W4Ta8PhQWQ673GhOgJIEbHhzhMV8104AytZc8YlxHqUd8ZQaMYY9mur6dq5gpe3QQggwpUm8BrmPIxn9cKWMNpNIQRUEK8yMdPZXdVLvL5TA15NwF2o6qKGlxk+OzQ0/KUN4NVoWxXVfADf5xvpcLVdTOB7W+WDIr+nRAoWCvGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041640; c=relaxed/simple; bh=Fk8T9wjTQs/tbyNOKyUAwa1q1KGR3r3K5TeJZkiMBYU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=sESyQlpoLz/HrjRFOaCojTFmpwxBAznalYTCeDgjBlAYO12tEJ/t4CbYqDzzwTVAC6cxXPodiSWgBVnPDuGrhOJKVja8eN7eFL6qN399NYhSBHyBF/vXzu7pa370xjr2q20LGCC8Cia1wkNdf7upflxSOUTzbElDEwczg15T4Zo= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700041639; x=1731577639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Fk8T9wjTQs/tbyNOKyUAwa1q1KGR3r3K5TeJZkiMBYU=; b=akEtIAAhWJcbiDcCh5yR/LYEnX2wJkQhNf50xpkJ0nWncULOYQs1bDnK rrIr/SNbErlzIH26yNbSQE4mTht2Qpn8zx699CHQDqytsdQC6QKBBL7EE jXFyLyEtKMCoPULqY53W1fo1v9lZIkSRgpofKrbkWRFipK8HfGIXf/pG5 F1Rs4NzXJKyV95I95S6E0AjA80VmGGqVVBK37WvJEwFuKynWTOKToXgS9 X81RthHp9+WoF35CnWd7VmDZIJam7PIS+vE0o0XuVLQaZelK7VjMEgOQM 10fFz0vi9lpoO5ePSCPLmtRwSc8bt5m3ptlZPHs8vZrvAZGbXQD35zcuw Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="457342613" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="457342613" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2023 01:47:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="938431712" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="938431712" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 15 Nov 2023 01:47:13 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id CF9021005687; Wed, 15 Nov 2023 17:47:05 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 16/16] [APX NDD] Support APX NDD for cmove insns Date: Wed, 15 Nov 2023 17:47:05 +0800 Message-Id: <20231115094705.3976553-17-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231115094705.3976553-1-hongyu.wang@intel.com> References: <20231115094705.3976553-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782623063877453558 X-GMAIL-MSGID: 1782623063877453558 gcc/ChangeLog: * config/i386/i386.md (*movcc_noc): Extend with new constraints to support NDD. (*movsicc_noc_zext): Likewise. (*movsicc_noc_zext_1): Likewise. (*movqicc_noc): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-ndd-cmov.c: New test. --- gcc/config/i386/i386.md | 48 ++++++++++++-------- gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c | 16 +++++++ 2 files changed, 45 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2e3d37d08b0..2ae9aaf59fb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -24119,47 +24119,56 @@ (define_split (neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))]) (define_insn "*movcc_noc" - [(set (match_operand:SWI248 0 "register_operand" "=r,r") + [(set (match_operand:SWI248 0 "register_operand" "=r,r,r,r") (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand:SWI248 2 "nonimmediate_operand" "rm,0") - (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))] + (match_operand:SWI248 2 "nonimmediate_operand" "rm,0,rm,r") + (match_operand:SWI248 3 "nonimmediate_operand" "0,rm,r,rm")))] "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "@ cmov%O2%C1\t{%2, %0|%0, %2} - cmov%O2%c1\t{%3, %0|%0, %3}" - [(set_attr "type" "icmov") + cmov%O2%c1\t{%3, %0|%0, %3} + cmov%O2%C1\t{%2, %3, %0|%0, %3, %2} + cmov%O2%c1\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "isa" "*,*,apx_ndd,apx_ndd") + (set_attr "type" "icmov") (set_attr "mode" "")]) (define_insn "*movsicc_noc_zext" - [(set (match_operand:DI 0 "register_operand" "=r,r") + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") (if_then_else:DI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "rm,0")) + (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r")) (zero_extend:DI - (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))] + (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))] "TARGET_64BIT && TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "@ cmov%O2%C1\t{%2, %k0|%k0, %2} - cmov%O2%c1\t{%3, %k0|%k0, %3}" - [(set_attr "type" "icmov") + cmov%O2%c1\t{%3, %k0|%k0, %3} + cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2} + cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}" + [(set_attr "isa" "*,*,apx_ndd,apx_ndd") + (set_attr "type" "icmov") (set_attr "mode" "SI")]) (define_insn "*movsicc_noc_zext_1" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r") (zero_extend:DI (if_then_else:SI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand:SI 2 "nonimmediate_operand" "rm,0") - (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))] + (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm,r") + (match_operand:SI 3 "nonimmediate_operand" "0,rm,r,rm"))))] "TARGET_64BIT && TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "@ cmov%O2%C1\t{%2, %k0|%k0, %2} - cmov%O2%c1\t{%3, %k0|%k0, %3}" - [(set_attr "type" "icmov") + cmov%O2%c1\t{%3, %k0|%k0, %3} + cmov%O2%C1\t{%2, %3, %k0|%k0, %3, %2} + cmov%O2%c1\t{%3, %2, %k0|%k0, %2, %3}" + [(set_attr "isa" "*,*,apx_ndd,apx_ndd") + (set_attr "type" "icmov") (set_attr "mode" "SI")]) @@ -24184,14 +24193,15 @@ (define_split }) (define_insn "*movqicc_noc" - [(set (match_operand:QI 0 "register_operand" "=r,r") + [(set (match_operand:QI 0 "register_operand" "=r,r,r") (if_then_else:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand:QI 2 "register_operand" "r,0") - (match_operand:QI 3 "register_operand" "0,r")))] + (match_operand:QI 2 "register_operand" "r,0,r") + (match_operand:QI 3 "register_operand" "0,r,r")))] "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL" "#" - [(set_attr "type" "icmov") + [(set_attr "isa" "*,*,apx_ndd") + (set_attr "type" "icmov") (set_attr "mode" "QI")]) (define_split diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c new file mode 100644 index 00000000000..459dc965342 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -m64 -mapxf" } */ +/* { dg-final { scan-assembler-times "cmove\[^\n\r]*, %eax" 1 } } */ +/* { dg-final { scan-assembler-times "cmovge\[^\n\r]*, %eax" 1 } } */ + +unsigned int c[4]; + +unsigned long long foo1 (int a, unsigned int b) +{ + return a ? b : c[1]; +} + +unsigned int foo3 (int a, int b, unsigned int c, unsigned int d) +{ + return a < b ? c : d; +}