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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z6-20020a0cfec6000000b0065b282ad457si8506575qvs.168.2023.11.15.01.43.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 01:43:57 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Dkw7Rjr4; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C538A38582A1 for ; Wed, 15 Nov 2023 09:43:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 5E6633858C98 for ; Wed, 15 Nov 2023 09:43:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5E6633858C98 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5E6633858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.136 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041414; cv=none; b=prikcTCQNnCPeyijDNI5BHzXjj3SSZLrlNBUe/4pT/R+b3+tKWDkLMSpuPt2uHgwrl3REJ1QpVKk/7MX5WnvsCFW0MdO1HOO4OtL/Bwo+e3PrKZHBBK6vEYl+3ceE0K2WCMuY3xXxq6AYHoUkn+ulFl+wpyQ3NY4ghqm99fvLwk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041414; c=relaxed/simple; bh=aeomDttvkDrwtJxGvr5H2HO1bEqNxZ1/PAxJiHbPX4U=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=xl1cqSpvYiEIDonyxGX4WOjj6uV63FZKHcNHiU83Bap/RdaHoEapemsQAKOWp/EbaTUqaDbcdmMdwWDPnQZlGNl1CTspu8SC5RkTlqxaxV/S5lnhSHQ6yK3+6mckLTnLGbrvYu0kQ/LoyW9YJ8kg41WIlt+h+EbDEM3Y8JID/6U= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700041412; x=1731577412; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=aeomDttvkDrwtJxGvr5H2HO1bEqNxZ1/PAxJiHbPX4U=; b=Dkw7Rjr4S6dv7DlAFvhejX4dE6RVAmTIqY8M6TWzFbatasgesI3dX9uF MWOWoRNLKiSuFYRIu5Ie3g6hqVt6qMFUvuXEC4qp0lQkgGGQ6m1pR6PSO sMCJwSf4Hs5MSI09wseSI+BGjI7FiSefad9o5VhmJY2C3HSHVwR+ZoP+9 C9BxbH8Z89dJmS3uL9BWffw+0X6EzZuyhxgVTZLITdGNgnF+S4e9D/ick vsn8mU5Rw+VWjPJZ3HZxfXHmb+UvwsPuUZwen09mDCcMIKyApXGQJOIG6 LreAiI+QL7L4qIkSopyA+jebKZWA01snVOvrDx7eL+aGFSuEn3ltnlluH Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="370193985" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="370193985" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2023 01:43:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="758445964" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="758445964" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 15 Nov 2023 01:43:28 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id ADEAD1005674; Wed, 15 Nov 2023 17:43:27 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] [i386] APX: Fix EGPR usage in several patterns. Date: Wed, 15 Nov 2023 17:43:27 +0800 Message-Id: <20231115094327.3976469-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782622649729090775 X-GMAIL-MSGID: 1782622649729090775 Hi, For vextract/insert{if}128 they cannot adopt EGPR in their memory operand, all related pattern should be adjusted to disable EGPR usage on them. Also fix a wrong gpr16 attr for insertps. Bootstrapped/regtested on x86-64-pc-linux-gnu{-m32,} Ok for master? gcc/ChangeLog: * config/i386/sse.md (vec_extract_hi_): Add noavx512vl alternative with attr addr gpr16 and "jm" constraint. (vec_extract_hi_): Likewise for SF vector modes. (@vec_extract_hi_): Likewise. (*vec_extractv2ti): Likewise. (vec_set_hi_): Likewise. * config/i386/mmx.md (@sse4_1_insertps_): Correct gpr16 attr for each alternative. --- gcc/config/i386/mmx.md | 2 +- gcc/config/i386/sse.md | 32 ++++++++++++++++++++------------ 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a3d08bb9d3b..355538749d1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1215,7 +1215,7 @@ (define_insn "@sse4_1_insertps_" } } [(set_attr "isa" "noavx,noavx,avx") - (set_attr "addr" "*,*,gpr16") + (set_attr "addr" "gpr16,gpr16,*") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,1,*") (set_attr "prefix_extra" "1") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c502582102e..472c2190f89 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12049,9 +12049,9 @@ (define_insn "vec_extract_hi__mask" (set_attr "mode" "")]) (define_insn "vec_extract_hi_" - [(set (match_operand: 0 "nonimmediate_operand" "=vm") + [(set (match_operand: 0 "nonimmediate_operand" "=xjm,vm") (vec_select: - (match_operand:VI8F_256 1 "register_operand" "v") + (match_operand:VI8F_256 1 "register_operand" "x,v") (parallel [(const_int 2) (const_int 3)])))] "TARGET_AVX" { @@ -12065,7 +12065,9 @@ (define_insn "vec_extract_hi_" else return "vextract\t{$0x1, %1, %0|%0, %1, 0x1}"; } - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx512vl,avx512vl") + (set_attr "addr" "gpr16,*") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "vex") @@ -12132,7 +12134,7 @@ (define_insn "vec_extract_hi__mask" (set_attr "mode" "")]) (define_insn "vec_extract_hi_" - [(set (match_operand: 0 "nonimmediate_operand" "=xm, vm") + [(set (match_operand: 0 "nonimmediate_operand" "=xjm, vm") (vec_select: (match_operand:VI4F_256 1 "register_operand" "x, v") (parallel [(const_int 4) (const_int 5) @@ -12141,7 +12143,8 @@ (define_insn "vec_extract_hi_" "@ vextract\t{$0x1, %1, %0|%0, %1, 0x1} vextract32x4\t{$0x1, %1, %0|%0, %1, 0x1}" - [(set_attr "isa" "*, avx512vl") + [(set_attr "isa" "noavx512vl, avx512vl") + (set_attr "addr" "gpr16,*") (set_attr "prefix" "vex, evex") (set_attr "type" "sselog1") (set_attr "length_immediate" "1") @@ -12222,7 +12225,7 @@ (define_insn_and_split "@vec_extract_lo_" "operands[1] = gen_lowpart (mode, operands[1]);") (define_insn "@vec_extract_hi_" - [(set (match_operand: 0 "nonimmediate_operand" "=xm,vm") + [(set (match_operand: 0 "nonimmediate_operand" "=xjm,vm") (vec_select: (match_operand:V16_256 1 "register_operand" "x,v") (parallel [(const_int 8) (const_int 9) @@ -12236,7 +12239,8 @@ (define_insn "@vec_extract_hi_" [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "isa" "*,avx512vl") + (set_attr "isa" "noavx512vl,avx512vl") + (set_attr "addr" "gpr16,*") (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) @@ -20465,7 +20469,7 @@ (define_split }) (define_insn "*vec_extractv2ti" - [(set (match_operand:TI 0 "nonimmediate_operand" "=xm,vm") + [(set (match_operand:TI 0 "nonimmediate_operand" "=xjm,vm") (vec_select:TI (match_operand:V2TI 1 "register_operand" "x,v") (parallel @@ -20477,6 +20481,8 @@ (define_insn "*vec_extractv2ti" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") + (set_attr "isa" "noavx512vl,avx512vl") + (set_attr "addr" "gpr16,*") (set_attr "prefix" "vex,evex") (set_attr "mode" "OI")]) @@ -27556,12 +27562,12 @@ (define_insn "vec_set_lo_" (set_attr "mode" "")]) (define_insn "vec_set_hi_" - [(set (match_operand:VI8F_256 0 "register_operand" "=v") + [(set (match_operand:VI8F_256 0 "register_operand" "=x,v") (vec_concat:VI8F_256 (vec_select: - (match_operand:VI8F_256 1 "register_operand" "v") + (match_operand:VI8F_256 1 "register_operand" "x,v") (parallel [(const_int 0) (const_int 1)])) - (match_operand: 2 "nonimmediate_operand" "vm")))] + (match_operand: 2 "nonimmediate_operand" "xjm,vm")))] "TARGET_AVX && " { if (TARGET_AVX512DQ) @@ -27571,7 +27577,9 @@ (define_insn "vec_set_hi_" else return "vinsert\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"; } - [(set_attr "type" "sselog") + [(set_attr "isa" "noavx512vl,avx512vl") + (set_attr "addr" "gpr16,*") + (set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "vex")