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[8.43.85.97]) by mx.google.com with ESMTPS id f22-20020ac859d6000000b0041996c8044dsi4651550qtf.307.2023.11.13.06.28.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 06:28:35 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 43C86396C8FC for ; Mon, 13 Nov 2023 14:27:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3DFCA38618A2 for ; Mon, 13 Nov 2023 14:27:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3DFCA38618A2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3DFCA38618A2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699885646; cv=none; b=sRP7OROZyB03xwI9KvkXUMmuqKfl4WtM7YheIk05l2WWTrG0tKHEoJphzFZgNa0vVy2vL94ACnF/P74xcNUijfEYl1YoN6zwj/zuDp0d8J2KDYuh8ybDxQpJbGr0BhtX/dR5IiJGD0bJp8YkwNwPlSvGKUyGYc5ViNQhddbsFuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699885646; c=relaxed/simple; bh=WynT6Oq/B43Sc7si64hKZDvyIJx7OjTFXGvpijfQfSI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JnalE/9UjfXzM8tzKz4a46eGPbVm+VLG328CBHvT8zPBTHaJ91E/E+mA7ISDf8k/mHqbj214cBFvUlfAtJSnOZ6oH34Te702aCzQig0RxWGK5IwqlMg5k4mj6EGQio3ycuTofx9Vld2XizRSQWQa/zpqo8nDLFzDYLyC8KGtjd8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62414150C; Mon, 13 Nov 2023 06:28:10 -0800 (PST) Received: from e126323.arm.com (unknown [10.57.41.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 740D53F7B4; Mon, 13 Nov 2023 06:27:24 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed 02/22] arm: testsuite: correctly detect hard_float Date: Mon, 13 Nov 2023 14:26:38 +0000 Message-Id: <20231113142658.69039-3-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113142658.69039-1-rearnsha@arm.com> References: <20231113142658.69039-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-14.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782459364324584948 X-GMAIL-MSGID: 1782459364324584948 Add an arm-specific test to check_effective_target_hard_float for Arm to handle cases where we only have single-precision FP in hardware. gcc/testsuite: * lib/target-supports.exp (check_effective_target_hard_float): Add arm-specific test. --- gcc/testsuite/lib/target-supports.exp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index d414cddf4dc..ee173b9fb6b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1420,6 +1420,17 @@ proc check_effective_target_mpaired_single { args } { # Return true if the target has access to FPU instructions. proc check_effective_target_hard_float { } { + # This should work on cores that only have single-precision, + # and should also correctly handle legacy cores that had thumb1 and + # lacked FP support for that, but had it in Arm state. + if { [istarget arm*-*-*] } { + return [check_no_compiler_messages hard_float assembly { + #if __ARM_FP == 0 + #error __arm_soft_float + #endif + }] + } + if { [istarget loongarch*-*-*] } { return [check_no_compiler_messages hard_float assembly { #if (defined __loongarch_soft_float)