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[8.43.85.97]) by mx.google.com with ESMTPS id i13-20020ac85c0d000000b00421a4bd9022si4398766qti.231.2023.11.13.06.28.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 06:28:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 432953959C96 for ; Mon, 13 Nov 2023 14:27:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7A68F3856962 for ; Mon, 13 Nov 2023 14:27:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A68F3856962 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7A68F3856962 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699885645; cv=none; b=t1nKkystkdlzUfhMql7mmiTfmrhKWehY/z7RQAjH7EL7jAG03fVrFnrsqGMFKUj+LLaI2+fqzZjCOohBxdia6RolcxgZY2jhXPDfizgl75rql60KEUJ4aMxck50MMD1L6VQMvCEPHPO3jylQ8jT+YBH/jayKm1aF6PgrpwaVuqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699885645; c=relaxed/simple; bh=QkuyDKyH+q5L/BaLFgZGebBxEIIR1798FHr+3BpoxqA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=HtfX/ktQSjGvKKSPmdIKFBVhdoW4/a/Z/DczVH+KB6yTntuBSm13FtamU2Azow7Irrljvsqz0Ylbiut9Q/aO7IbSal1D2MVN+XZDYDA4Cwmn6j8jPNezUi+t9/rQdRb0+uEwrrxhVNWHxcDJZN3CtDbo4M6JA8dTCab6k3Cx2zU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6F8F1007; Mon, 13 Nov 2023 06:28:09 -0800 (PST) Received: from e126323.arm.com (unknown [10.57.41.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7D5B3F7B4; Mon, 13 Nov 2023 06:27:23 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed 01/22] arm: testsuite: correctly detect armv6t2 hardware for acle execution tests Date: Mon, 13 Nov 2023 14:26:37 +0000 Message-Id: <20231113142658.69039-2-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113142658.69039-1-rearnsha@arm.com> References: <20231113142658.69039-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-14.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782459361307975408 X-GMAIL-MSGID: 1782459361307975408 Some of the ACLE tests for Arm are executable, but we were only testing that the compiler could generate code for them, not that the hardware was capable of executing them. Fix this by adding an execution test for suitable hardware. gcc/testsuite: * lib/target-supports.exp (check_effective_target_arm_arch_v6t2_hw_ok): New function. * gcc.target/arm/acle/data-intrinsics-armv6.c: Use it. * gcc.target/arm/acle/data-intrinsics-rbit.c: Likewise. --- .../arm/acle/data-intrinsics-armv6.c | 2 +- .../gcc.target/arm/acle/data-intrinsics-rbit.c | 2 +- gcc/testsuite/lib/target-supports.exp | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-armv6.c b/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-armv6.c index 988ecac3787..6dc8c55e2f9 100644 --- a/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-armv6.c +++ b/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-armv6.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target arm_arch_v6t2_ok } */ +/* { dg-require-effective-target arm_arch_v6t2_hw_ok } */ /* { dg-add-options arm_arch_v6t2 } */ #include "arm_acle.h" diff --git a/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-rbit.c b/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-rbit.c index d1fe274b5ce..b01c4219a7e 100644 --- a/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-rbit.c +++ b/gcc/testsuite/gcc.target/arm/acle/data-intrinsics-rbit.c @@ -1,6 +1,6 @@ /* Test the ACLE data intrinsics existence for specific instruction. */ /* { dg-do run } */ -/* { dg-require-effective-target arm_arch_v6t2_ok } */ +/* { dg-require-effective-target arm_arch_v6t2_hw_ok } */ /* { dg-additional-options "--save-temps -O1" } */ /* { dg-add-options arm_arch_v6t2 } */ /* { dg-final { check-function-bodies "**" "" "" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 1a7bea96c1e..d414cddf4dc 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5590,6 +5590,24 @@ proc check_effective_target_arm_thumb1_cbz_ok {} { } } +# Return 1 if this is an Arm target which supports the Armv6t2 extensions. +# This can be either in Arm state or in Thumb state. + +proc check_effective_target_arm_arch_v6t2_hw_ok {} { + if [check_effective_target_arm_thumb1_ok] { + return [check_no_compiler_messages arm_movt object { + int + main (void) + { + asm ("bfc r0, #1, #2"); + return 0; + } + } [add_options_for_arm_arch_v6t2 ""]] + } else { + return 0 + } +} + # Return 1 if this is an ARM target where ARMv8-M Security Extensions is # available.