diff mbox series

[Committed] RISC-V: Adapt VLS init tests

Message ID 20231113120050.608605-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [Committed] RISC-V: Adapt VLS init tests |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Nov. 13, 2023, noon UTC 
  Realize that init tests are wrong by my previous mistakes.
Fix them and committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Fix init test.
	* gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto.

---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h    | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2e91b9a9664..9cc3656e710 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -437,7 +437,7 @@  typedef double v512df __attribute__ ((vector_size (4096)));
   void init_##TYPE1##_##TYPE2##_##NUM (VARS##NUM (TYPE2, __VA_ARGS__),         \
 				       TYPE2 *__restrict out)                  \
   {                                                                            \
-    TYPE1 v = {INIT##NUM (__VA_ARGS__)};                                       \
+    TYPE1 v = {__VA_ARGS__};                                                   \
     *(TYPE1 *) out = v;                                                        \
   }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
index aec2c6e5e5f..0f78ae0ebe2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
@@ -43,4 +43,4 @@  DEF_INIT (v128uqi, uint8_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
index f9c58aef553..f27c395441b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
@@ -45,4 +45,4 @@  DEF_INIT (v128uhi, uint16_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.vx} 494 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
index eb970c7b042..df15bd7300f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
@@ -24,4 +24,4 @@  DEF_INIT (v128hf, _Float16, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle16\.v} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
index fedeb445a2b..09bdbd19cc0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
@@ -45,4 +45,4 @@  DEF_INIT (v128usi, uint32_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
index c93ac524c88..65ca8cb41e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
@@ -23,4 +23,4 @@  DEF_INIT (v128sf, float, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 	  100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
 	  114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle32\.v} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
index 304539f4868..9cd36ce2ec1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
@@ -45,4 +45,4 @@  DEF_INIT (v128udi, uint64_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
index 4b966010dca..ad337054f3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
@@ -23,4 +23,4 @@  DEF_INIT (v128df, double, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 	  100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
 	  114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle64\.v} 7 } } */