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[8.43.85.97]) by mx.google.com with ESMTPS id b23-20020a05620a0f9700b00775cf5f88a2si2841266qkn.526.2023.11.12.06.54.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Nov 2023 06:54:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53AE43858028 for ; Sun, 12 Nov 2023 14:53:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 85ADD3856975 for ; Sun, 12 Nov 2023 14:53:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 85ADD3856975 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 85ADD3856975 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699800813; cv=none; b=LumaGKaTti/BWiDdd55GExdIzkv+XXzDl3MnUs8J5D1rISh69Pq1EjsS0Su7+HMe3iWZjKygBiNf98yageN2FnysLyiPNfCCMR2Ksn20sUmvAFGdvhlGT3qmriDV9HG0Tsa9x44gGT3ugHS9Xb0MPvTanxPGX8GZqTwE56rcNJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699800813; c=relaxed/simple; bh=aHUFMzZBQL59w/1ZnMB5/68951o93y/qtZOfX1dHfi4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=HQeKDXCgXlN5YjmfNHZir15UFzKSwleqt4IDDOhqbAAHL6IVm4TsRb+rRfFdUozUbj/rylHqtFhcy5YqfMOLKMulsJcVdxmOjP5bYbtQt0+cbVckFTqNQHHuToxz5g+yIH0Z6K/v0KFYKvA8p/YM9720s6hiX1fFp627QnH0GoA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A09ADA7; Sun, 12 Nov 2023 06:54:17 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A24133F7B4; Sun, 12 Nov 2023 06:53:31 -0800 (PST) From: Richard Sandiford To: jlaw@ventanamicro.com, vmakarov@redhat.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 5/5] Add an aligned_register_operand predicate Date: Sun, 12 Nov 2023 14:52:29 +0000 Message-Id: <20231112145229.2924713-6-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231112145229.2924713-1-richard.sandiford@arm.com> References: <20231112145229.2924713-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-23.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782370367762146205 X-GMAIL-MSGID: 1782370367762146205 This patch adds a target-independent aligned_register_operand predicate, for use with register constraints that use filters to impose an alignment. The definition deliberately jetisons some of the historical baggage in general_operand. gcc/ * common.md (aligned_register_operand): New predicate. --- gcc/common.md | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/gcc/common.md b/gcc/common.md index 51ecd79786b..91a72bd7731 100644 --- a/gcc/common.md +++ b/gcc/common.md @@ -17,6 +17,34 @@ ;; along with GCC; see the file COPYING3. If not see ;; . */ +;; This predicate is intended to be paired with register constraints that use +;; register filters to impose an alignment. Operands that are aligned via +;; TARGET_HARD_REGNO_MODE_OK should use normal register_operands instead. +(define_predicate "aligned_register_operand" + (match_code "reg,subreg") +{ + /* Require the offset in a non-paradoxical subreg to be naturally aligned. + For example, if we have a subreg of something that is double the size of + this operand, the offset must select the first or second half of it. */ + if (SUBREG_P (op) + && multiple_p (SUBREG_BYTE (op), GET_MODE_SIZE (GET_MODE (op)))) + op = SUBREG_REG (op); + if (!REG_P (op)) + return false; + + if (HARD_REGISTER_P (op)) + { + if (!in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op))) + return false; + + /* Reject hard registers that would need reloading, so that the reload + is visible to IRA and to pre-RA optimizers. */ + if (REGNO (op) % REG_NREGS (op) != 0) + return false; + } + return true; +}) + (define_register_constraint "r" "GENERAL_REGS" "Matches any general register.")