Message ID | 20231109120038.109612-1-juzhe.zhong@rivai.ai |
---|---|
State | Accepted |
Headers | |
Series | [Committed] RISC-V: Add PR112450 test to avoid regression | |
Checks
Context | Check | Description |
---|---|---|
snail/gcc-patch-check | success | Github commit url |
Commit Message
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c new file mode 100644 index 00000000000..964a4d34e3d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 --param=riscv-autovec-lmul=m8 -fno-vect-cost-model" } */ + +int a, b, d, e; +short c; +void f() { + for (; e; e++) { + int g = 6; + for (; g > 2; g--) { + int i = -8; + while (i < 20) { + i += 5; + a += b; + } + c *= d; + } + b--; + } +}