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[8.43.85.97]) by mx.google.com with ESMTPS id bp41-20020a05620a45a900b0077429d89227si2660977qkb.375.2023.11.08.23.15.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Nov 2023 23:15:28 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ns5j0d1V; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7BE43385828E for ; Thu, 9 Nov 2023 07:15:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by sourceware.org (Postfix) with ESMTPS id 6BB743858D1E for ; Thu, 9 Nov 2023 07:15:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6BB743858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6BB743858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699514103; cv=none; b=ngYNVlIqJKrQVin1BqKeUh5lo5TWhcw+9wgWvVUxbyfJjXYUAxfjg1KyacqFJM1TiQ4txa+F9tkjxqWJbn93xxo76tCZgiA2NBqg7WsVRO/15TZOfzR/peQuHj0Gx9+9ykuleVSknloGIYA9kCyiZkFlnMLGXkVICdm4QYbmU+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699514103; c=relaxed/simple; bh=eP6OT+hXdNfQsqCKMgJvFFEdnW5gR+5PHObA2q9RQTY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=SIBRIz8O989fbXKjE9QrVJtIljmCjNsxWWIvw5vm9qjtkJMiLT6dLUbCm4xgZCHEmtyel6XIfCFtbx6vhpBUTCi1r4q0g8RvtsffbybyeqH4BLOz5nkZTv/fNOKQp3BkD5p/su9l8BJpLe/1/DQjF77njn60ATQ/Mr4ej8DIEZE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699514102; x=1731050102; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=eP6OT+hXdNfQsqCKMgJvFFEdnW5gR+5PHObA2q9RQTY=; b=Ns5j0d1Vw7Ag1Z2nMDZ61NGKtxYtCg2vyUXd792OdzkM1YQn+MwzbxGR ZNrYZcUJD+4t5hjBWjkVKB/ag5+u5vRYTHlxUSSGv4UFMSvfwL/N6caIB Mfiy3MjgM8NKBMySGI01qKpMmg0nmMr3VpTFdXBOidQ5ZGK8CF/DUjKdV cezleKDmHkW8QI3fq+Vjfp5nN7VmOvMoKBEAXNC2p49dquXZfViImNGGv QVv0R6DtXsD+y7XBqn0Leuz5AEtOzPpAQvxT0JnDRlxxjayZkMpQJNl8B 9VVivqSGxflQyQdUlCRrKPBqptssy/R9A0KBlHWJY+ZGOh9aopxGPrlfm Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="8580719" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="8580719" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2023 23:15:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="833743162" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="833743162" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 08 Nov 2023 23:14:58 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9875110056F2; Thu, 9 Nov 2023 15:14:57 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] Avoid generate vblendps with ymm16+ Date: Thu, 9 Nov 2023 15:14:57 +0800 Message-Id: <20231109071457.2574044-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782069727033277055 X-GMAIL-MSGID: 1782069727033277055 This patch aims to avoid generate vblendps with ymm16+, And have bootstrapped and tested on x86_64-pc-linux-gnu{-m32,-m64}. Ok for trunk? gcc/ChangeLog: PR target/112435 * config/i386/sse.md: Adding constraints to restrict the generation of vblendps. gcc/testsuite/ChangeLog: PR target/112435 * gcc.target/i386/pr112435-1.c: New test. * gcc.target/i386/pr112435-2.c: Ditto. * gcc.target/i386/pr112435-3.c: Ditto. --- gcc/config/i386/sse.md | 28 +++++--- gcc/testsuite/gcc.target/i386/pr112435-1.c | 14 ++++ gcc/testsuite/gcc.target/i386/pr112435-2.c | 64 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr112435-3.c | 79 ++++++++++++++++++++++ 4 files changed, 175 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr112435-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr112435-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr112435-3.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 33198756bb0..666f931c88d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -19254,7 +19254,8 @@ mask = INTVAL (operands[3]) / 2; mask |= (INTVAL (operands[5]) - 4) / 2 << 1; operands[3] = GEN_INT (mask); - if (INTVAL (operands[3]) == 2 && !) + if (INTVAL (operands[3]) == 2 && ! + && !x86_evex_reg_mentioned_p (operands, 3)) return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; return "vshuf64x2\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } @@ -19414,7 +19415,8 @@ mask |= (INTVAL (operands[7]) - 8) / 4 << 1; operands[3] = GEN_INT (mask); - if (INTVAL (operands[3]) == 2 && !) + if (INTVAL (operands[3]) == 2 && ! + && !x86_evex_reg_mentioned_p (operands, 3)) return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; return "vshuf32x4\t{%3, %2, %1, %0|%0, %1, %2, %3}"; @@ -26776,10 +26778,13 @@ else return "vmovaps\t{%2, %0|%0, %2}"; } - if ((mask & 0xbb) == 18) - return "vblendps\t{$15, %2, %1, %0|%0, %1, %2, 15}"; - if ((mask & 0xbb) == 48) - return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; + if (!x86_evex_reg_mentioned_p (operands, 3)) + { + if ((mask & 0xbb) == 18) + return "vblendps\t{$15, %2, %1, %0|%0, %1, %2, 15}"; + if ((mask & 0xbb) == 48) + return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; + } return "vperm2i128\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } [(set_attr "type" "sselog") @@ -27433,10 +27438,13 @@ && avx_vperm2f128_parallel (operands[3], mode)" { int mask = avx_vperm2f128_parallel (operands[3], mode) - 1; - if ((mask & 0xbb) == 0x12) - return "vblendps\t{$15, %2, %1, %0|%0, %1, %2, 15}"; - if ((mask & 0xbb) == 0x30) - return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; + if (!x86_evex_reg_mentioned_p (operands, 3)) + { + if ((mask & 0xbb) == 0x12) + return "vblendps\t{$15, %2, %1, %0|%0, %1, %2, 15}"; + if ((mask & 0xbb) == 0x30) + return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}"; + } if ((mask & 0xbb) == 0x20) return "vinsert\t{$1, %x2, %1, %0|%0, %1, %x2, 1}"; operands[3] = GEN_INT (mask); diff --git a/gcc/testsuite/gcc.target/i386/pr112435-1.c b/gcc/testsuite/gcc.target/i386/pr112435-1.c new file mode 100644 index 00000000000..ff56523b4e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112435-1.c @@ -0,0 +1,14 @@ +/* PR target/112435 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Ofast -march=sapphirerapids" } */ +/* { dg-final { scan-assembler-not "vblendps" } } */ + +#include + +__m256i +f(__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_shuffle_i32x4 (t, b, 2); +} diff --git a/gcc/testsuite/gcc.target/i386/pr112435-2.c b/gcc/testsuite/gcc.target/i386/pr112435-2.c new file mode 100644 index 00000000000..27ba80b1e68 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112435-2.c @@ -0,0 +1,64 @@ +/* PR target/112435 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Ofast -march=sapphirerapids" } */ +/* { dg-final { scan-assembler-not "vblendps.*ymm17\$" } } */ + +#include + +/* Vpermi128/Vpermf128 */ +__m256i +perm0 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_permute2x128_si256 (t, b, 50); +} + +__m256i +perm1 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_permute2x128_si256 (t, b, 18); +} + +__m256i +perm2 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_permute2x128_si256 (t, b, 48); +} + +/* vshuf{i,f}{32x4,64x2} ymm .*/ +__m256i +shuff0 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_shuffle_i32x4(t, b, 2); +} + +__m256 +shuff1 (__m256 a, __m256 b) +{ + register __m256 t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_shuffle_f32x4(t, b, 2); +} + +__m256i +shuff2 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_shuffle_i64x2(t, b, 2); +} + +__m256d +shuff3 (__m256d a, __m256d b) +{ + register __m256d t __asm__("ymm17") = a; + asm("":"+v"(t)); + return _mm256_shuffle_f64x2(t, b, 2); +} diff --git a/gcc/testsuite/gcc.target/i386/pr112435-3.c b/gcc/testsuite/gcc.target/i386/pr112435-3.c new file mode 100644 index 00000000000..f39820d4f37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112435-3.c @@ -0,0 +1,79 @@ +/* PR target/112435 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Ofast -march=sapphirerapids" } */ +/* { dg-final { scan-assembler-not "vblendps.*ymm17\$" } } */ + +#include + +/* Vpermf128 */ +__m256 +perm0 (__m256 a, __m256 b) +{ + register __m256 t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_ps (t, b, 50); +} + +__m256 +perm1 (__m256 a, __m256 b) +{ + register __m256 t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_ps (t, b, 18); +} + +__m256 +perm2 (__m256 a, __m256 b) +{ + register __m256 t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_ps (t, b, 48); +} + +__m256i +perm3 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_si256 (t, b, 50); +} + +__m256i +perm4 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_si256 (t, b, 18); +} + +__m256i +perm5 (__m256i a, __m256i b) +{ + register __m256i t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_si256 (t, b, 48); +} + +__m256d +perm6 (__m256d a, __m256d b) +{ + register __m256d t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_pd (t, b, 50); +} + +__m256d +perm7 (__m256d a, __m256d b) +{ + register __m256d t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_pd (t, b, 18); +} + +__m256d +perm8 (__m256d a, __m256d b) +{ + register __m256d t __asm__("ymm17") =a; + asm("":"+v"(t)); + return _mm256_permute2f128_pd (t, b, 48); +}