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bh=pnTctBQe+C91dJSpFcaZX61wy8ziDziud3AdbvexBXs=; b=B9DoWTkHi0suqtqZkQvUcXxwh1jwidP7QSWXOtZy7ZF4AZ3PK3UuVN+IqTQ5CC8yvc IVC9Xs1PYwuNHBn+fiGQmIPxkyotMej6wtzncoRF2vdfZZpzQNgZDY9rlCXQb7XXwc/V z92KCJq1jyitSOk3q4CTRO4mFf8tfIdYR22xlpPLnyjAOQnEzHIUx0baDnRIcPibhM60 NRopeVCU2353TtKKuT1XHNgTZC/7DG7GGzWJEr8QRxTgibT2iP+of1Mw4AtKORl2XcJK sORFSqi54/YI3FTP38Tpt1FMr+kCAKT4k7wMH+K1ft0hcGvE7wzTJxheWZgr4LKiUk50 lblg== X-Gm-Message-State: AOJu0YyukFLRu0RA4+k5ci9jxr12g8O4iKtcgY95FAt0cjtnb2w8lbY1 eWQx6VdH88IKZATJqkAty9XIt8Z9TdfEIsmfeSLFJg== X-Received: by 2002:a05:651c:154c:b0:2c5:1eb6:bd1e with SMTP id y12-20020a05651c154c00b002c51eb6bd1emr2057447ljp.43.1699441774892; Wed, 08 Nov 2023 03:09:34 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id g4-20020a05600c310400b004068e09a70bsm18903289wmo.31.2023.11.08.03.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Nov 2023 03:09:34 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Wed, 8 Nov 2023 11:09:13 +0000 Message-Id: <20231108110914.2710021-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231108110914.2710021-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781993901479841799 X-GMAIL-MSGID: 1781993901479841799 gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index be66b1428a7..0109e1836cf 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT"