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[8.43.85.97]) by mx.google.com with ESMTPS id m18-20020a05620a291200b0076cb26a4d93si6720311qkp.233.2023.11.06.23.50.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 23:50:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 66E9E38555B9 for ; Tue, 7 Nov 2023 07:50:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 330A83858D35 for ; Tue, 7 Nov 2023 07:49:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 330A83858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 330A83858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699343386; cv=none; b=u3SfsV5gAW+AFUlt81sbPFm09LUlolZKo+FgbQwbbOrX8dJCwTtp1QSP6kRjQXRfoLwaZLgG3XBxAJrgkyayNwWEl3FQcHVqbpxgMykWFmdcI0wljGjM7tBLGN3jpa+GZW2+LjPg+PPNs4VIdmkI2vLOWx/eFwt7TCzTIoadlPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699343386; c=relaxed/simple; bh=ksB2vxEod29J8jSOqjGKcHm0kVJC+pjvaEblTPC0mLg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=pseFPZLbhZDrBuzQ9VobOir3d5Sgvhjt6+PV6+M+hB+DnRovEjO6SaBXOfV4eVH5sKnUl2iYrxJ6gPAAOedILm0+yuaOdhbrZdfeKpez5EASM5uFlxf02p07XzsVvefl7/RlxO1KX+n3MdGLw5nfAGRcvSODCHxMWhzgKXTUX9A= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1699343374tjhi2djf Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Nov 2023 15:49:33 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: ueooV2Tl7JnQLg21tSpGoDNjuf/ZKigDxp9W1vJ1a74cKHglmTpJvnS8mMPqY eHCWwn6+IzAU+dYsCawqI3a9Ig7Hluzy+J1e9aWHbm0Z7sRRYCxyKprpBGrXkBP3m7ncgIN 65QB8PHFkHUXZ+r4A7rC5hDTdFwrR986pLucgvYpFrGeZjoCByRZpox5aW2ThhlwQQUhjBS bHMe+MFyZitICUfocMpztRZVFdRDtIx/l6TZvD+Mlckq0ByI5fv86gSMHfQ6bQ+5QlAC0Wn 62CmoODEBYzLEaUPtTdoajjzFDhEZ/C/Oyz6LQtlcCC8qbNe3n/DkGpGNYaR9QQMTPWhue1 VCJKK4EUqJWFJRqI2hZ8caZQSI7w7NDDZ6rkO1OxeWz+3vtU2deM/SbvNuydw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 1941631198748558296 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Fixed failed rvv combine testcases Date: Tue, 7 Nov 2023 15:49:33 +0800 Message-Id: <20231107074933.4025916-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781890714667236929 X-GMAIL-MSGID: 1781890714667236929 Hi, This patch fixed the fellowing failed testcases on the trunk: FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c scan-assembler-times \\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2 ... FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c scan-assembler-times \\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 ... The reason for these failed testcases is the introduce of .VCOND_MASK_LEN in midend for other bugfix and further leads to a new vcond_mask_len rtl pattern after expand. So we need add new combine patterns handle this case. Consider this code: int16_t foo (int8_t *restrict a, int8_t *restrict pred) { int16_t sum = 0; for (int i = 0; i < 16; i += 1) if (pred[i]) sum += a[i]; return sum; } Before this patch: foo: vsetivli zero,16,e8,m1,ta,ma vle8.v v0,0(a1) vsetvli a5,zero,e8,m1,ta,ma vmsne.vi v0,v0,0 vsetvli zero,zero,e16,m2,ta,ma li a3,0 vmv.v.i v2,0 vsetivli zero,16,e16,m2,ta,ma vle8.v v6,0(a0),v0.t vmv.s.x v1,a3 vsetvli a5,zero,e16,m2,ta,ma vsext.vf2 v4,v6 vsetivli zero,16,e16,m2,tu,ma vmerge.vvm v2,v2,v4,v0 vsetvli a5,zero,e16,m2,ta,ma vredsum.vs v2,v2,v1 vmv.x.s a0,v2 slliw a0,a0,16 sraiw a0,a0,16 ret After this patch: foo: vsetivli zero,16,e16,m2,ta,ma li a5,0 vle8.v v0,0(a1) vmv.s.x v1,a5 vsetvli zero,zero,e8,m1,ta,ma vmsne.vi v0,v0,0 vle8.v v2,0(a0),v0.t vwredsum.vs v1,v2,v1,v0.t vsetvli zero,zero,e16,m1,ta,ma vmv.x.s a0,v1 slliw a0,a0,16 sraiw a0,a0,16 ret Combine the vsext.vf2, vmerge.vvm, and vredsum.vs instructions while reducing the corresponding vsetvl instructions. gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_len_): New combine pattern. (*cond_len_): Ditto. (*cond_len_): Ditto. (*cond_len_extend): Ditto. (*cond_len_widen_reduc_plus_scal_): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: --- gcc/config/riscv/autovec-opt.md | 214 ++++++++++++++++++ .../rvv/autovec/cond/cond_widen_reduc-1.c | 13 +- .../rvv/autovec/cond/cond_widen_reduc-2.c | 30 +-- 3 files changed, 232 insertions(+), 25 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index d0f8b3cde4e..3c87e66ea49 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -194,6 +194,84 @@ } [(set_attr "type" "vector")]) +;; Combine sign_extend/zero_extend(vf2) and vcond_mask_len +(define_insn_and_split "*cond_len_" + [(set (match_operand:VWEXTI 0 "register_operand") + (if_then_else:VWEXTI + (unspec: + [(match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (vec_merge:VWEXTI + (any_extend:VWEXTI (match_operand: 2 "register_operand")) + (match_operand:VWEXTI 1 "vector_merge_operand") + (match_operand: 3 "register_operand")) + (match_dup 1)))] + "TARGET_VECTOR" + "#" + "&& 1" + [(const_int 0)] +{ + emit_insn (gen_pred__vf2 (operands[0], operands[3], operands[1], operands[2], + operands[4], operands[5], operands[6], CONST0_RTX (Pmode))); + DONE; +} +[(set_attr "type" "vector")]) + +;; Combine sign_extend/zero_extend(vf4) and vcond_mask_len +(define_insn_and_split "*cond_len_" + [(set (match_operand:VQEXTI 0 "register_operand") + (if_then_else:VQEXTI + (unspec: + [(match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (vec_merge:VQEXTI + (any_extend:VQEXTI (match_operand: 2 "register_operand")) + (match_operand:VQEXTI 1 "vector_merge_operand") + (match_operand: 3 "register_operand")) + (match_dup 1)))] + "TARGET_VECTOR" + "#" + "&& 1" + [(const_int 0)] +{ + emit_insn (gen_pred__vf4 (operands[0], operands[3], operands[1], operands[2], + operands[4], operands[5], operands[6], CONST0_RTX (Pmode))); + DONE; +} +[(set_attr "type" "vector")]) + +;; Combine sign_extend/zero_extend(vf8) and vcond_mask_len +(define_insn_and_split "*cond_len_" + [(set (match_operand:VOEXTI 0 "register_operand") + (if_then_else:VOEXTI + (unspec: + [(match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (vec_merge:VOEXTI + (any_extend:VOEXTI (match_operand: 2 "register_operand")) + (match_operand:VOEXTI 1 "vector_merge_operand") + (match_operand: 3 "register_operand")) + (match_dup 1)))] + "TARGET_VECTOR" + "#" + "&& 1" + [(const_int 0)] +{ + emit_insn (gen_pred__vf8 (operands[0], operands[3], operands[1], operands[2], + operands[4], operands[5], operands[6], CONST0_RTX (Pmode))); + DONE; +} +[(set_attr "type" "vector")]) + ;; Combine trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" [(set (match_operand: 0 "register_operand") @@ -235,6 +313,32 @@ } [(set_attr "type" "vector")]) +;; Combine FP extend(vf2) and vcond_mask_len +(define_insn_and_split "*cond_len_extend" + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand") + (if_then_else:VWEXTF_ZVFHMIN + (unspec: + [(match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (vec_merge:VWEXTF_ZVFHMIN + (float_extend:VWEXTF_ZVFHMIN (match_operand: 2 "register_operand")) + (match_operand:VWEXTF_ZVFHMIN 1 "vector_merge_operand") + (match_operand: 3 "register_operand")) + (match_dup 1)))] + "TARGET_VECTOR" + "#" + "&& 1" + [(const_int 0)] +{ + emit_insn (gen_pred_extend (operands[0], operands[3], operands[1], operands[2], + operands[4], operands[5], operands[6], CONST0_RTX (Pmode))); + DONE; +} +[(set_attr "type" "vector")]) + ;; Combine FP trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" [(set (match_operand: 0 "register_operand") @@ -1151,6 +1255,61 @@ } [(set_attr "type" "vector")]) +;; Combine mask_len_extend + vredsum to mask_vwredsum[u] +;; where the mrege of mask_len_extend is vector const 0 +(define_insn_and_split "*cond_len_widen_reduc_plus_scal_" + [(set (match_operand: 0 "register_operand") + (unspec: [ + (if_then_else: + (unspec: [ + (match_operand 2 "vector_length_operand") + (const_int 0) + (const_int 0) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (vec_merge: + (any_extend: + (match_operand:VI_QHS_NO_M8 3 "register_operand")) + (if_then_else: + (unspec: [ + (match_operand: 4 "vector_all_trues_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_1_or_2_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_operand: 9 "vector_const_0_operand") + (match_operand: 10 "vector_merge_operand")) + (match_operand: 1 "register_operand")) + (if_then_else: + (unspec: [ + (match_dup 4) + (match_dup 5) + (match_dup 6) + (match_dup 7) + (match_dup 8) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_dup 9) + (match_dup 10))) + ] UNSPEC_REDUC_SUM))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + rtx ops[] = {operands[0], operands[3], operands[1], operands[2]}; + riscv_vector::expand_reduction (, + riscv_vector::REDUCE_OP_M, + ops, CONST0_RTX (mode)); + DONE; +} +[(set_attr "type" "vector")]) + ;; Combine mask_extend + vfredsum to mask_vfwredusum ;; where the mrege of mask_extend is vector const 0 (define_insn_and_split "*cond_widen_reduc_plus_scal_" @@ -1187,6 +1346,61 @@ } [(set_attr "type" "vector")]) +;; Combine mask_len_extend + vredsum to mask_vwredsum[u] +;; where the mrege of mask_len_extend is vector const 0 +(define_insn_and_split "*cond_len_widen_reduc_plus_scal_" + [(set (match_operand: 0 "register_operand") + (unspec: [ + (if_then_else: + (unspec: [ + (match_operand 2 "vector_length_operand") + (const_int 0) + (const_int 0) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (vec_merge: + (float_extend: + (match_operand:VF_HS_NO_M8 3 "register_operand")) + (if_then_else: + (unspec: [ + (match_operand: 4 "vector_all_trues_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_1_or_2_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_operand: 9 "vector_const_0_operand") + (match_operand: 10 "vector_merge_operand")) + (match_operand: 1 "register_operand")) + (if_then_else: + (unspec: [ + (match_dup 4) + (match_dup 5) + (match_dup 6) + (match_dup 7) + (match_dup 8) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_dup 9) + (match_dup 10))) + ] UNSPEC_REDUC_SUM_UNORDERED))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + rtx ops[] = {operands[0], operands[3], operands[1], operands[2]}; + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, + riscv_vector::REDUCE_OP_M_FRM_DYN, + ops, CONST0_RTX (mode)); + DONE; +} +[(set_attr "type" "vector")]) + ;; ============================================================================= ;; Misc combine patterns ;; ============================================================================= diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c index 22a71048684..47889f3a1cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c @@ -15,16 +15,27 @@ #define TEST_ALL(TEST) \ TEST (int16_t, int8_t, 16) \ + TEST (int32_t, int8_t, 8) \ TEST (int32_t, int16_t, 8) \ + TEST (int64_t, int8_t, 4) \ + TEST (int64_t, int16_t, 4) \ TEST (int64_t, int32_t, 4) \ TEST (uint16_t, uint8_t, 16) \ + TEST (uint32_t, uint8_t, 8) \ TEST (uint32_t, uint16_t, 8) \ + TEST (uint64_t, uint8_t, 4) \ + TEST (uint64_t, uint16_t, 4) \ TEST (uint64_t, uint32_t, 4) \ TEST (float, _Float16, 8) \ + TEST (double, _Float16, 4) \ TEST (double, float, 4) TEST_ALL (TEST_TYPE) -/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvwredsum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvwredsumu\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c index 7c8fedd072b..662d1351215 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c @@ -1,30 +1,12 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ -#include -#define TEST_TYPE(TYPE1, TYPE2, N) \ - __attribute__ ((noipa)) \ - TYPE1 reduc_##TYPE1##_##TYPE2 (TYPE2 *restrict a, TYPE2 *restrict pred) \ - { \ - TYPE1 sum = 0; \ - for (int i = 0; i < N; i += 1) \ - if (pred[i]) \ - sum += a[i]; \ - return sum; \ - } +#include "cond_widen_reduc-1.c" -#define TEST_ALL(TEST) \ - TEST (int16_t, int8_t, 16) \ - TEST (int32_t, int16_t, 8) \ - TEST (int64_t, int32_t, 4) \ - TEST (uint16_t, uint8_t, 16) \ - TEST (uint32_t, uint16_t, 8) \ - TEST (uint64_t, uint32_t, 4) \ - TEST (float, _Float16, 8) \ - TEST (double, float, 4) - -TEST_ALL (TEST_TYPE) - -/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvwredsum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvwredsumu\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */