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[8.43.85.97]) by mx.google.com with ESMTPS id bq33-20020a05620a46a100b0077a4af9271esi7139444qkb.294.2023.11.06.23.33.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 23:34:00 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SHWzGQcM; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CAFF8385C420 for ; Tue, 7 Nov 2023 07:33:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 259D53858D35 for ; Tue, 7 Nov 2023 07:33:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 259D53858D35 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 259D53858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699342414; cv=none; b=CsivUCW71z671cWuUHdYmkZz/iVrzAbSMBCk1txRbc2Nl8OU/XFBS+qvnRdyZ74CqtkZGz5FAavFcr3H1I6DNu+okYklenzploEIEeft0RqxvoUVuq1bSuSUnhHMW+LC5K8S2yGD1n/R+vcd2fWwt+914kyqj6Cq7HugudjABDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699342414; c=relaxed/simple; bh=dn/eZJanDf6gcJuGGqMAHF0c3mkHlQfbzwZgTHq/4CU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=cFjesxuKg81OMq7QQx389d4hLY1P8kzj0y7BD8Rs2YLDLG5E4+47nlmWqfuaVV0D31odozqE7/GhI6DRMvwmAoU5eOk038e9u45czGYegl7IQetDGvIlsinNY+Iy6kFoFORODL3YuhUM0FA1rEPx1cU5CoV4ewRReN11mczpEek= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699342406; x=1730878406; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=dn/eZJanDf6gcJuGGqMAHF0c3mkHlQfbzwZgTHq/4CU=; b=SHWzGQcM4701yL0omTHTUgfABRz/g5GxANLMw3TYXr/5LV+mVtWlsuw3 cz0Dv/iho4VxRh/flYXscn2ZRF6Qz9GIW09NYF9EkyiUEpLwSq/CKZdmY 0qf4S7qX31ApWF2YN33auwEoZNxBEp2vdLTUMpQiTs2pIzA2Jd5U4voLV ZsaUEJTDU5iv8aCKzGWtJfrQ8IfNJbCf0aTXF6TelrPTwrhTzEi8Lv6nq ltIHqDsZ4vpJbms8f1h1tjXSwksXMSZdAZyQfMThIiS4u7FUw8VWEi89P B6N/pznubUUi8hp+PQ0sxcVIvRPV8KQ5inxj6K2wEKIC6XQVaeUk5umch Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="10993861" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="10993861" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 23:33:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="936062058" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="936062058" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 06 Nov 2023 23:33:22 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A563D1005669; Tue, 7 Nov 2023 15:33:21 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] [i386] APX: Fix ICE due to movti postreload splitter [PR112394] Date: Tue, 7 Nov 2023 15:33:21 +0800 Message-Id: <20231107073321.479349-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781889698484775604 X-GMAIL-MSGID: 1781889698484775604 Hi, When APX EGPR enabled, the TImode move pattern *movti_internal allows move between gpr and sse reg using constraint pair ("r","Yd"). Then a post-reload splitter transform such move to vec_extractv2di, while under -msse4.1 -mno-avx EGPR is not allowed for its enabled alternative, which caused ICE that insn does not match the constraint. To prevent such ICE, we need to adjust the constraint correspond to "Yd". Add a new "jc" constraint to disable EGPR under -mno-avx. Bootstrapped and regtseted on x86_64-pc-linux-gnu{-m32,}. OK for trunk? gcc/ChangeLog: PR target/112394 * config/i386/constraints.md (jc): New constraint that prohibits EGPR on -mno-avx. * config/i386/i386.md (*movdi_internal): Change r constraint corresponds to Yd. (*movti_internal): Likewise. gcc/testsuite/ChangeLog: PR target/112394 * gcc.target/i386/pr112394.c: New test. --- gcc/config/i386/constraints.md | 3 +++ gcc/config/i386/i386.md | 8 ++++---- gcc/testsuite/gcc.target/i386/pr112394.c | 24 ++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr112394.c diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index f6275740eb2..74c2f0f2d32 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -434,3 +434,6 @@ (define_address_constraint "jb" (and (match_operand 0 "vsib_address_operand") (not (and (match_test "TARGET_APX_EGPR") (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_register_constraint "jc" + "TARGET_APX_EGPR && !TARGET_AVX ? GENERAL_GPR16 : GENERAL_REGS") diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ecc74e9994e..ec39c2dd512 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2454,8 +2454,8 @@ (define_insn "*movoi_internal_avx" (set_attr "mode" "OI")]) (define_insn "*movti_internal" - [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd") - (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,r"))] + [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?jc,?Yd") + (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,jc"))] "(TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))) || (TARGET_SSE @@ -2537,9 +2537,9 @@ (define_split (define_insn "*movdi_internal" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,?Yv,?v,?v,m ,m,?r ,?*Yd,?r,?v,?*y,?*x,*k,*k ,*r,*m,*k") + "=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,?Yv,?v,?v,m ,m,?jc,?*Yd,?r,?v,?*y,?*x,*k,*k ,*r,*m,*k") (match_operand:DI 1 "general_operand" - "riFo,riF,Z,rem,i,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,v,*Yd,r ,?v,r ,*x ,*y ,*r,*kBk,*k,*k,CBC"))] + "riFo,riF,Z,rem,i,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,v,*Yd,jc ,?v,r ,*x ,*y ,*r,*kBk,*k,*k,CBC"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && ix86_hardreg_mov_ok (operands[0], operands[1])" { diff --git a/gcc/testsuite/gcc.target/i386/pr112394.c b/gcc/testsuite/gcc.target/i386/pr112394.c new file mode 100644 index 00000000000..c582f6ea6bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112394.c @@ -0,0 +1,24 @@ +/* PR target/112394 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-msse4.1 -m64 -O -mapxf" } */ + +typedef int __attribute__((__vector_size__ (8))) A; +typedef int __attribute__((__vector_size__ (16))) B; +typedef char __attribute__((__vector_size__ (4))) C; +typedef char __attribute__((__vector_size__ (32))) D; +typedef _Complex __int128 CU; +typedef _Float16 __attribute__((__vector_size__ (8))) F; +D d; +B b; +CU gcu; + +int +foo (char c, int, int, int, int, CU cu, int x) +{ + d /= c | d; + F f = __builtin_convertvector (b, F); + cu /= gcu; + A a = (A) f; + int i = cu + x; + return ((C) a[0])[1] + i + c; +}