[v1] LoongArch: Add modifiers for lsx and lasx.
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gcc/ChangeLog:
* doc/extend.texi:Added modifiers for LoongArch architecture
lsx and lasx in the manual.
---
gcc/doc/extend.texi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
Comments
On Tue, 2023-11-07 at 12:06 +0800, chenxiaolong wrote:
> +__m128i a,b,c;
> +
> +__asm__ ("vadd.d %w0,%w1,%w2\n\t"
> + :"=f" (c)
> + :"f" (a),"f" (b)
> + :"cc");
This example does not work for me, with the definition of __m128i in
another patch:
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
__m128i a,b,c;
void t(void) {
__asm__ ("vadd.d %w0,%w1,%w2\n\t"
:"=f" (c)
:"f" (a),"f" (b)
:"cc");
}
t1.c: In function ‘t’:
t1.c:6:1: error: inconsistent operand constraints in an ‘asm’
6 | __asm__ ("vadd.d %w0,%w1,%w2\n\t"
Please recheck.
On Tue, 2023-11-07 at 19:10 +0800, Xi Ruoyao wrote:
> On Tue, 2023-11-07 at 12:06 +0800, chenxiaolong wrote:
> > +__m128i a,b,c;
> > +
> > +__asm__ ("vadd.d %w0,%w1,%w2\n\t"
> > + :"=f" (c)
> > + :"f" (a),"f" (b)
> > + :"cc");
>
> This example does not work for me, with the definition of __m128i in
> another patch:
>
> typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
>
> __m128i a,b,c;
>
> void t(void) {
> __asm__ ("vadd.d %w0,%w1,%w2\n\t"
> :"=f" (c)
> :"f" (a),"f" (b)
> :"cc");
> }
>
> t1.c: In function ‘t’:
> t1.c:6:1: error: inconsistent operand constraints in an ‘asm’
> 6 | __asm__ ("vadd.d %w0,%w1,%w2\n\t"
>
> Please recheck.
Sorry, I didn't added -mlasx :(.
@@ -10582,6 +10582,31 @@ __asm__ ("btsl %2,%1\n\t" // Turn on zero-based bit #Offset in Base.
return old;
@end example
+In this LoongArch example, c (referred to in the template string as %0) is the
+output,and a (%1) and b (%2) are the inputs.Where the symbol "=f" refers to the
+use of a floating-point register as a constraint for the output type, and the
+"f" in the input operand refers to the use of a floating-point register operand,
+the constraint can refer to the definition of constraints in gcc.
+
+This is a 128-bit double-byte vector addition instruction,the instruction
+modifier (w) represents the 128-bit vector instruction modification format,its
+corresponding output instructions are @code{"vadd.d $vr0,$vr0,$vr1"}.
+
+On the @code{LoongArch} architecture, the operand can only output the
+corresponding vector (SX/ASX) instruction if it uses @code{'w}' and @code{'u'}
+in the assembly instruction,with @code{'f'} as the constraint character.
+
+@example
+__m128i a,b,c;
+
+__asm__ ("vadd.d %w0,%w1,%w2\n\t"
+ :"=f" (c)
+ :"f" (a),"f" (b)
+ :"cc");
+
+return c;
+@end example
+
Operands are separated by commas. Each operand has this format:
@example
@@ -11680,6 +11705,8 @@ The list below describes the supported modifiers and their effects for LoongArch
@item @code{m} @tab Same as @code{c}, but the printed value is @code{operand - 1}.
@item @code{X} @tab Print a constant integer operand in hexadecimal.
@item @code{z} @tab Print the operand in its unmodified form, followed by a comma.
+@item @code{u} @tab Print a LASX register.
+@item @code{w} @tab Print a LSX register.
@end multitable
@anchor{riscvOperandmodifiers}