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[8.43.85.97]) by mx.google.com with ESMTPS id a14-20020ac85b8e000000b00419628da454si5720531qta.177.2023.11.06.06.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 06:13:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3C9BE3856964 for ; Mon, 6 Nov 2023 14:13:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id B3B803858C2C for ; Mon, 6 Nov 2023 14:12:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3B803858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B3B803858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.194.254.142 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699279983; cv=none; b=sbw0KWue0X80aroNQtg8NLQ4aK/x2xE9qahI8AV4kBnEgkNKdt6MkLwkO7jy6gBJvHC8YVF5MdBHNTS63CxD4ftguFJAnr0epW9PVW8nO26ob+JNjO6fjeh8iA/uIHd/yAabAehHG+xt6dj+rrjVDz2VxKLGSu65c0FPLbZpEHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699279983; c=relaxed/simple; bh=UbMm9wocqWzsMl8YDsC/aPLMCc9kTun3wABsK+yB+Wo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=GdkGldRlxC9GzutzvAy7lx6PHI3y5UJWYIWm+z9D7FeTTW1qoLWIitr+rft1G8KMiFFj+EqtiOiqzl0VbepAC/9vv9wNSuLBhtECvR/aPbHgl4tWfOanYdnp1It57CQjSvEkOr+p3J3z2etdT/J+vQhxlrOrqdjQYQX9HCV5+s0= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp86t1699279970txlmsh38 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Nov 2023 22:12:49 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBflkOcxHxQh9W+oppvR1JjQG4yGQqmfAJKgxmcDXe5/ORh6qEx3Uc LSJajBwrdlaKvLQwatSwzZBXO/ED3VaKUSj2YBzPkW5G9Rr7jxv4XT6LQ5KqVczQj8FVuyc 7NypvkCkhAw66x8bsaeghRmvGNG5Uj2tO4ylL/pDWkY5JKo3NLcBgCXHrl+IqLdJkCXzAr+ xb361KoJYNvl/O2+Ayur93UA9/phDzCGZ86TJLRjpHkrMRBJgagd5V7vY1fa0RvhXN0Bd8b xndeMLRhvy+Y0RlpF/j6UeXr1hBV07EFvvMITKKvHnhlj5chtyiOP3tdz50EX7VPQ33nyd0 8fcCyjuNLahP8Wdmh4GZDmUu/lXZIox2d+ciQZa/NQAkf/bM00a2iXmMfCVlmlQyi0C998K XKJkTKJ9+wnP71RmJ/80c+gXAIGJfwAu X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8751828827903238775 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Early expand DImode vec_duplicate in RV32 system Date: Mon, 6 Nov 2023 22:12:48 +0800 Message-Id: <20231106141248.1378051-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781817558876260784 X-GMAIL-MSGID: 1781824232203177240 An ICE was discovered in recent rounding autovec support: config/riscv/riscv-v.cc:4314 65 | } | ^ 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, rtx_def*, bool) /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-v.cc:4314 0x1fb1aa2 pre_vsetvl::remove_avl_operand() /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3342 0x1fb18c1 pre_vsetvl::cleaup() /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3308 0x1fb216d pass_vsetvl::lazy_vsetvl() /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3480 0x1fb2214 pass_vsetvl::execute(function*) /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3504 The root cause is that the RA reload into (set (reg) vec_duplicate:DI). However, it is not valid in RV32 system since we don't have a single broadcast instruction DI scalar in RV32 system. We should expand it early for RV32 system. gcc/ChangeLog: * config/riscv/predicates.md: Adapt predicate. * config/riscv/riscv-protos.h (can_be_broadcasted_p): New function. * config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto. * config/riscv/vector.md (vec_duplicate): New pattern. (*vec_duplicate): Adapt vec_duplicate insn pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c: New test. --- gcc/config/riscv/predicates.md | 9 +----- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 20 +++++++++++++ gcc/config/riscv/vector.md | 20 ++++++++++++- .../riscv/rvv/autovec/unop/sew64-rv32.c | 29 +++++++++++++++++++ 5 files changed, 70 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index db18054607f..df1c66f3a76 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -553,14 +553,7 @@ ;; The scalar operand can be directly broadcast by RVV instructions. (define_predicate "direct_broadcast_operand" - (and (match_test "!(reload_completed && !FLOAT_MODE_P (GET_MODE (op)) - && (register_operand (op, GET_MODE (op)) || CONST_INT_P (op) - || rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))) - && maybe_gt (GET_MODE_BITSIZE (GET_MODE (op)), GET_MODE_BITSIZE (Pmode)))") - (ior (match_test "rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))") - (ior (match_code "const_int,const_poly_int") - (ior (match_operand 0 "register_operand") - (match_test "satisfies_constraint_Wdm (op)")))))) + (match_test "riscv_vector::can_be_broadcasted_p (op)")) ;; A CONST_INT operand that has exactly two bits cleared. (define_predicate "const_nottwobits_operand" diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 9b254a4b278..135df1a1d94 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -598,6 +598,7 @@ uint8_t get_sew (rtx_insn *); enum vlmul_type get_vlmul (rtx_insn *); int count_regno_occurrences (rtx_insn *, unsigned int); bool imm_avl_p (machine_mode); +bool can_be_broadcasted_p (rtx); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index ff9539fff02..6b8b4da7477 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4418,4 +4418,24 @@ count_regno_occurrences (rtx_insn *rinsn, unsigned int regno) return count; } +/* Return true if the OP can be directly broadcasted. */ +bool +can_be_broadcasted_p (rtx op) +{ + machine_mode mode = GET_MODE (op); + /* We don't allow RA (register allocation) reload generate + (vec_duplicate:DI reg) in RV32 system wheras we allow + (vec_duplicate:DI mem) in RV32 system. */ + if (!can_create_pseudo_p () && !FLOAT_MODE_P (mode) + && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (Pmode)) + && !satisfies_constraint_Wdm (op)) + return false; + + if (satisfies_constraint_K (op) || register_operand (op, mode) + || satisfies_constraint_Wdm (op) || rtx_equal_p (op, CONST0_RTX (mode))) + return true; + + return can_create_pseudo_p () && nonmemory_operand (op, mode); +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 8509c4fe5f2..e23f64938b7 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1370,11 +1370,29 @@ ;; ---- Duplicate Operations ;; ----------------------------------------------------------------- +(define_expand "vec_duplicate" + [(set (match_operand:V_VLS 0 "register_operand") + (vec_duplicate:V_VLS + (match_operand: 1 "direct_broadcast_operand")))] + "TARGET_VECTOR" + { + /* Early expand DImode broadcast in RV32 system to avoid RA reload + generate (set (reg) (vec_duplicate:DI)). */ + if (maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (Pmode))) + { + riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (mode), + riscv_vector::UNARY_OP, operands); + DONE; + } + /* Otherwise, allow it fall into general vec_duplicate pattern + which allow us to have vv->vx combine optimization in later pass. */ + }) + ;; According to GCC internal: ;; This pattern only handles duplicates of non-constant inputs. ;; Constant vectors go through the movm pattern instead. ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT. -(define_insn_and_split "vec_duplicate" +(define_insn_and_split "*vec_duplicate" [(set (match_operand:V_VLS 0 "register_operand") (vec_duplicate:V_VLS (match_operand: 1 "direct_broadcast_operand")))] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c new file mode 100644 index 00000000000..8f81369030e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +int64_t out[ARRAY_SIZE]; +int64_t ref[ARRAY_SIZE]; + +TEST_UNARY_CALL_CVT (float, int64_t, __builtin_llrintf) +TEST_ASSERT (int64_t) + + +TEST_INIT_CVT (float, __builtin_inf (), int64_t, __builtin_llrintf (__builtin_inff ()), 19) +TEST_INIT_CVT (float, -__builtin_inf (), int64_t, __builtin_llrintf (-__builtin_inff ()), 20) +TEST_INIT_CVT (float, __builtin_nanf (""), int64_t, 0x7fffffffffffffff, 21) + +int +main () +{ + RUN_TEST_CVT (float, int64_t, 19, __builtin_llrintf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int64_t, 20, __builtin_llrintf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int64_t, 21, __builtin_llrintf, in, out, ref, ARRAY_SIZE); + + return 0; +}