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[8.43.85.97]) by mx.google.com with ESMTPS id w19-20020a05620a445300b00777449886basi3997371qkp.572.2023.11.01.20.15.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 20:15:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=P7Da3tt3; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D0A943858430 for ; Thu, 2 Nov 2023 03:15:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 09D8A3858D39 for ; Thu, 2 Nov 2023 03:14:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 09D8A3858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 09D8A3858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.65 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698894898; cv=none; b=fDa4TFICk0UPgoY5905S9n2tdhrRxKTdjf0saLdtZdTdxQYnP6DJ/4Sj3iTdzOd2F3ep0fV2hEsZ65/QhzHT8irKtB8lvY63mwXwgdA8C+DECdb3tXVcQplaeO5tfTDj4tLqE7j7kvXM53z1y5daGkj0JyjnZBLL9rQnDoqro1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698894898; c=relaxed/simple; bh=6TTu9WObofnjQicv3+ZYPcOLmJ97ueGqy8H8m5f27/Q=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ayqUgYjztcInEYauEsJu1WKhS7aqFtpOGEIVcgjwhOgpQBDt9a2/2hEETtyRsqSUKHHoGlzjcebPjDq6ordXcuG115BX8nNUdrWfZuyStxo6WJDOkiSysKSpUhtKbz7gRc5jRj/iY2fGll6+SKzSvBAuRDubDq1SeBoNzVjcbJA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698894888; x=1730430888; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6TTu9WObofnjQicv3+ZYPcOLmJ97ueGqy8H8m5f27/Q=; b=P7Da3tt3cC2G7cc6Qcsda76Jx2PlldpP3lqrUzaDIv5gxQtiSKRqkVwy BkyElgllcEJjk3J4j9CbmfBC1n73Sk9Woou3SAcHKBV/rwMyFRkonoAYD AnzHvqwotBfUj+el7ddRR1TcCMSEBRjwLS8hhafMEMkVOU0vmOFm/jv1U rMKK1jh/xqPwHK1ld50uTeJGdx69I4UC/aRuHz5mXk+rM43Yl6ytjjV7H FMwzggeGsPkLVeilQdq/1CK4BmGX5WeoocW2JvzKDDnrGfG15v7SGjZ3s GuKvpYQkUuZ6u3ax3LIYevEGk7n5j098ii97D91AeVKxG6wsvF1IyTRQU Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10881"; a="392511800" X-IronPort-AV: E=Sophos;i="6.03,270,1694761200"; d="scan'208";a="392511800" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2023 20:14:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10881"; a="878089578" X-IronPort-AV: E=Sophos;i="6.03,270,1694761200"; d="scan'208";a="878089578" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga002.fm.intel.com with ESMTP; 01 Nov 2023 20:14:25 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 361DD10056AB; Thu, 2 Nov 2023 11:14:24 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com, jeffreyalaw@gmail.com, richard.sandiford@arm.com Subject: [PATCH v1] EXPMED: Allow vector mode for DSE extract_low_bits [PR111720] Date: Thu, 2 Nov 2023 11:14:23 +0800 Message-Id: <20231102031423.3751965-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781420442614173457 X-GMAIL-MSGID: 1781420442614173457 From: Pan Li The extract_low_bits only try the scalar mode if the bitsize of the mode and src_mode is not equal. When vector mode is given from get_stored_val in DSE, it will always fail and return NULL_RTX. This patch would like to allow the vector mode in the extract_low_bits if and only if the size of mode is less than or equals to the size of the src_mode. Given below example code with --param=riscv-autovec-preference=fixed-vlmax. vuint8m1_t test () { uint8_t arr[32] = { 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, }; return __riscv_vle8_v_u8m1(arr, 32); } Before this patch: test: lui a5,%hi(.LANCHOR0) addi sp,sp,-32 addi a5,a5,%lo(.LANCHOR0) li a3,32 vl2re64.v v2,0(a5) vsetvli zero,a3,e8,m1,ta,ma vs2r.v v2,0(sp) <== Unnecessary store to stack vle8.v v1,0(sp) <== Ditto vs1r.v v1,0(a0) addi sp,sp,32 jr ra After this patch: test: lui a5,%hi(.LANCHOR0) addi a5,a5,%lo(.LANCHOR0) li a4,32 addi sp,sp,-32 vsetvli zero,a4,e8,m1,ta,ma vle8.v v1,0(a5) vs1r.v v1,0(a0) addi sp,sp,32 jr ra Below tests are passed within this patch: * The x86 bootstrap and regression test. * The aarch64 regression test. * The risc-v regression test. PR target/111720 gcc/ChangeLog: * expmed.cc (extract_low_bits): Allow vector mode if the mode size is less than or equal to src_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111720-0.c: New test. * gcc.target/riscv/rvv/base/pr111720-1.c: New test. * gcc.target/riscv/rvv/base/pr111720-10.c: New test. * gcc.target/riscv/rvv/base/pr111720-2.c: New test. * gcc.target/riscv/rvv/base/pr111720-3.c: New test. * gcc.target/riscv/rvv/base/pr111720-4.c: New test. * gcc.target/riscv/rvv/base/pr111720-5.c: New test. * gcc.target/riscv/rvv/base/pr111720-6.c: New test. * gcc.target/riscv/rvv/base/pr111720-7.c: New test. * gcc.target/riscv/rvv/base/pr111720-8.c: New test. * gcc.target/riscv/rvv/base/pr111720-9.c: New test. Signed-off-by: Pan Li --- gcc/expmed.cc | 44 ++++++++++++------- .../gcc.target/riscv/rvv/base/pr111720-0.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-1.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-10.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-2.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-3.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-4.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-5.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-6.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-7.c | 21 +++++++++ .../gcc.target/riscv/rvv/base/pr111720-8.c | 18 ++++++++ .../gcc.target/riscv/rvv/base/pr111720-9.c | 15 +++++++ 12 files changed, 227 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c diff --git a/gcc/expmed.cc b/gcc/expmed.cc index b294eabb08d..5db83fe638c 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -2403,8 +2403,6 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode, rtx extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src) { - scalar_int_mode int_mode, src_int_mode; - if (mode == src_mode) return src; @@ -2437,22 +2435,38 @@ extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src) return x; } - if (!int_mode_for_mode (src_mode).exists (&src_int_mode) - || !int_mode_for_mode (mode).exists (&int_mode)) - return NULL_RTX; + if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (src_mode)) + { + if (maybe_gt (GET_MODE_BITSIZE (mode), GET_MODE_BITSIZE (src_mode)) + || !targetm.modes_tieable_p (mode, src_mode)) + return NULL_RTX; - if (!targetm.modes_tieable_p (src_int_mode, src_mode)) - return NULL_RTX; - if (!targetm.modes_tieable_p (int_mode, mode)) - return NULL_RTX; + /* For vector mode, only the bitsize (mode) <= bitsize (src_mode) and + tieable is allowed here. */ + src = gen_lowpart (mode, src); + } + else + { + scalar_int_mode int_mode, src_int_mode; - src = gen_lowpart (src_int_mode, src); - if (!validate_subreg (int_mode, src_int_mode, src, - subreg_lowpart_offset (int_mode, src_int_mode))) - return NULL_RTX; + if (!int_mode_for_mode (src_mode).exists (&src_int_mode) + || !int_mode_for_mode (mode).exists (&int_mode)) + return NULL_RTX; + + if (!targetm.modes_tieable_p (src_int_mode, src_mode)) + return NULL_RTX; + if (!targetm.modes_tieable_p (int_mode, mode)) + return NULL_RTX; + + src = gen_lowpart (src_int_mode, src); + if (!validate_subreg (int_mode, src_int_mode, src, + subreg_lowpart_offset (int_mode, src_int_mode))) + return NULL_RTX; + + src = convert_modes (int_mode, src_int_mode, src, true); + src = gen_lowpart (mode, src); + } - src = convert_modes (int_mode, src_int_mode, src, true); - src = gen_lowpart (mode, src); return src; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c new file mode 100644 index 00000000000..a61e94a6d98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c new file mode 100644 index 00000000000..46efd7379ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c new file mode 100644 index 00000000000..8bebac219a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool4_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vlm_v_b4(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c new file mode 100644 index 00000000000..47e4243e02e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 16); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c new file mode 100644 index 00000000000..5331e547ed3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 8); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c new file mode 100644 index 00000000000..0c728f93514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8mf2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8mf2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c new file mode 100644 index 00000000000..ccfc40cd382 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 4); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c new file mode 100644 index 00000000000..ce7ddbb99b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m8(arr, 32); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c new file mode 100644 index 00000000000..ac0100a1211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + vuint8m1_t varr = __riscv_vle8_v_u8m1(arr, 32); + vuint8m1_t vand_m = __riscv_vand_vx_u8m1(varr, 1, 32); + + return __riscv_vreinterpret_v_u8m1_b8(vand_m); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c new file mode 100644 index 00000000000..b7ebef80954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t test () { + float arr[32] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + }; + + return __riscv_vle32_v_f32m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c new file mode 100644 index 00000000000..21fed06d201 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat64m8_t test () { + double arr[8] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + }; + + return __riscv_vle64_v_f64m8(arr, 4); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */