From patchwork Tue Oct 31 06:37:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 159976 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b90f:0:b0:403:3b70:6f57 with SMTP id t15csp47812vqg; Mon, 30 Oct 2023 23:39:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8djFRjl/FOjVHb6fmIEyodYexUwYpiN0lEjF5+X6dhENJUR8WQQysLg3mZvfEH8t/9AIW X-Received: by 2002:a25:d411:0:b0:da0:c64f:ea10 with SMTP id m17-20020a25d411000000b00da0c64fea10mr10775013ybf.43.1698734377962; Mon, 30 Oct 2023 23:39:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698734377; cv=pass; d=google.com; s=arc-20160816; b=tREXVJNC+HWHEFOQKc3UJmvCOUV2pOefoCaa8hzMqKiGrKtV/SJ3MPKopaH25GL22y uCz9Uw00aCNk1KITW4IyWWqA0QLUaDIjdS/s1mW2EQUgRvDSeEsStgT+KO9FLdFyn0/M bZ5do+5I4QMww6uDFEAAYeUQKwAnGf0wpvQ2MC1oXO3ufFDV/aaawTGjD1SNPaEXgu1C 1hCp1RRZ3pFuvXdH9KhYTufECn82THH7W69EO2AYkm7kpZxUkQCKnPXbZcrh1PojyZkY 7Xw3JO3p/btR50HzC12tIu28SAk32Wx1iXMTDNElSUDPhtIuNHokL/SuxWO8RejYeOv+ RkuA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=IcFf3bQGsiRmX/j4uoP4lCqRmPdZRM8TzLT7UrsLBDY=; fh=n8eNxIWSYJwy/CU3QSXzDvE/zeEoomCGojuOcYEQEyQ=; b=HnhAtKGL7FeTqchNV6afKDAWKkh7nPSk3iAkkXEOEGGA0FfOyizFttZhG2XN1InlXG KRaIBYt5oR6amcqEUoBcT22b0fLN93a326yGEkZ0pzaHXx5NHBIyifbuLkqNc9SQBu6q bBwCe29B1tO+2DiuM9+hHrndfe7ReZ7B82MfosfrGZfi+9BFIwJE59V9T2m1fgu6jUDi j97jEEyoZBqk12tcrufO1jXjZOQTnxte8kDWWFdk5DW1QmDn7e/tab+RPUXteYRDHU0a SpHz75RiXYLtD4RrVp6E3DaJ6zGufbacmKmZvZwp9u4xytSYgaxKBKEM5yvixBHiWU6a r18w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MzKv91B8; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id t5-20020a0cef05000000b00670a182453esi521358qvr.299.2023.10.30.23.39.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 23:39:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MzKv91B8; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AEA33385841B for ; Tue, 31 Oct 2023 06:39:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 8774E3858D38 for ; Tue, 31 Oct 2023 06:39:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8774E3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8774E3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.88 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698734353; cv=none; b=s1DvGN/wkSRVmnuSd2E3WPIeFPRCgTmCAC4R5j69je5COarhV6WuG/KDqDUmhdFtTCTwAYCwWVU5qnXjbtWJS31y2kSE2nR0n5T61AMoO+yajUPlvhu1xgkRbeeZkC9av0WwrII3txcFEG8KqGUv1qOPGCw/J7SOUNVNDktj3k4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698734353; c=relaxed/simple; bh=9mYHFUCcTugwsgM4oMVMEiyk9SucH/ifTM+ExxqbyzI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qBA3v5obXD7jQtzdiOzozd//jgHQX0T66owu0XZPYrDy9h+LEQyHYSKmT5H48qSTR3HAjRpndL1+JWI9g9q+iOmG499NPYjvFQGuX+dCWDjQu3kInoLDCpjnPSkRvUOn6RLaASVyNizGwMFAOQ1mxxqJGaxTrR7achF/hPVzw6E= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698734350; x=1730270350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9mYHFUCcTugwsgM4oMVMEiyk9SucH/ifTM+ExxqbyzI=; b=MzKv91B8h41/nc3Ghg0K7IAHFaBjT1jVZUYEaIWJX1BFbFX2DHWZbWSb gujZHI8lN3jH6bxlxttIfCAcscn026mEHdSycd9HafZDfOSx2wz1Bjoxh 6g6X78CctUBkGhUxSO44C5T0m2COIPT+w5O7en1SL97njmPCb8amPSMd4 Lte6skVoq0EGkAX0jmtIByRE2+Su+2sPlNTHm74o9HZsMt+Mi8vxRFtXt CkJq/xpnj7K3Fx03j6YNiqHebJrFTfHEN64Piwr+EU7HAbFjDQ1w+jfdT Jc9emfI4JwQq738+UvJrh7gZsa+yA52OOrcPgfdyQGC4g7v1Ksk5wg0Av Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="419335305" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="419335305" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2023 23:39:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="710328692" X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="710328692" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 30 Oct 2023 23:39:06 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B4E0E100567E; Tue, 31 Oct 2023 14:39:05 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 4/4] Push no-evex512 target for 128/256 bit intrins Date: Tue, 31 Oct 2023 14:37:03 +0800 Message-Id: <20231031063703.2643896-5-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231031063703.2643896-1-haochen.jiang@intel.com> References: <20231031063703.2643896-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781252098711721036 X-GMAIL-MSGID: 1781252098711721036 gcc/ChangeLog: PR target/111889 * config/i386/avx512bf16intrin.h: Push no-evex512 target. * config/i386/avx512bf16vlintrin.h: Ditto. * config/i386/avx512bitalgvlintrin.h: Ditto. * config/i386/avx512bwintrin.h: Ditto. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/avx512fp16intrin.h: Ditto. * config/i386/avx512fp16vlintrin.h: Ditto. * config/i386/avx512ifmavlintrin.h: Ditto. * config/i386/avx512vbmi2vlintrin.h: Ditto. * config/i386/avx512vbmivlintrin.h: Ditto. * config/i386/avx512vlbwintrin.h: Ditto. * config/i386/avx512vldqintrin.h: Ditto. * config/i386/avx512vlintrin.h: Ditto. * config/i386/avx512vnnivlintrin.h: Ditto. * config/i386/avx512vp2intersectvlintrin.h: Ditto. * config/i386/avx512vpopcntdqvlintrin.h: Ditto. gcc/testsuite/ChangeLog: PR target/111889 * gcc.target/i386/pr111889.c: New test. --- gcc/config/i386/avx512bf16intrin.h | 4 ++-- gcc/config/i386/avx512bf16vlintrin.h | 4 ++-- gcc/config/i386/avx512bitalgvlintrin.h | 4 ++-- gcc/config/i386/avx512bwintrin.h | 4 ++-- gcc/config/i386/avx512dqintrin.h | 4 ++-- gcc/config/i386/avx512fintrin.h | 4 ++-- gcc/config/i386/avx512fp16intrin.h | 4 ++-- gcc/config/i386/avx512fp16vlintrin.h | 4 ++-- gcc/config/i386/avx512ifmavlintrin.h | 4 ++-- gcc/config/i386/avx512vbmi2vlintrin.h | 4 ++-- gcc/config/i386/avx512vbmivlintrin.h | 4 ++-- gcc/config/i386/avx512vlbwintrin.h | 4 ++-- gcc/config/i386/avx512vldqintrin.h | 4 ++-- gcc/config/i386/avx512vlintrin.h | 6 +++--- gcc/config/i386/avx512vnnivlintrin.h | 4 ++-- gcc/config/i386/avx512vp2intersectvlintrin.h | 5 +++-- gcc/config/i386/avx512vpopcntdqvlintrin.h | 5 +++-- gcc/testsuite/gcc.target/i386/pr111889.c | 10 ++++++++++ 18 files changed, 47 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr111889.c diff --git a/gcc/config/i386/avx512bf16intrin.h b/gcc/config/i386/avx512bf16intrin.h index 94ccbf6389f..5084a8c23ed 100644 --- a/gcc/config/i386/avx512bf16intrin.h +++ b/gcc/config/i386/avx512bf16intrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BF16INTRIN_H_INCLUDED #define _AVX512BF16INTRIN_H_INCLUDED -#ifndef __AVX512BF16__ +#if !defined (__AVX512BF16__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512bf16") +#pragma GCC target("avx512bf16,no-evex512") #define __DISABLE_AVX512BF16__ #endif /* __AVX512BF16__ */ diff --git a/gcc/config/i386/avx512bf16vlintrin.h b/gcc/config/i386/avx512bf16vlintrin.h index 78c001f55ad..a389bfe7cec 100644 --- a/gcc/config/i386/avx512bf16vlintrin.h +++ b/gcc/config/i386/avx512bf16vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BF16VLINTRIN_H_INCLUDED #define _AVX512BF16VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512BF16__) +#if !defined(__AVX512VL__) || !defined(__AVX512BF16__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512bf16,avx512vl") +#pragma GCC target("avx512bf16,avx512vl,no-evex512") #define __DISABLE_AVX512BF16VL__ #endif /* __AVX512BF16__ */ diff --git a/gcc/config/i386/avx512bitalgvlintrin.h b/gcc/config/i386/avx512bitalgvlintrin.h index 39301625601..327425ef0cb 100644 --- a/gcc/config/i386/avx512bitalgvlintrin.h +++ b/gcc/config/i386/avx512bitalgvlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BITALGVLINTRIN_H_INCLUDED #define _AVX512BITALGVLINTRIN_H_INCLUDED -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) +#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512bitalg,avx512vl") +#pragma GCC target("avx512bitalg,avx512vl,no-evex512") #define __DISABLE_AVX512BITALGVL__ #endif /* __AVX512BITALGVL__ */ diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h index 45a46936aef..d5ce79fd073 100644 --- a/gcc/config/i386/avx512bwintrin.h +++ b/gcc/config/i386/avx512bwintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BWINTRIN_H_INCLUDED #define _AVX512BWINTRIN_H_INCLUDED -#ifndef __AVX512BW__ +#if !defined (__AVX512BW__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512bw") +#pragma GCC target("avx512bw,no-evex512") #define __DISABLE_AVX512BW__ #endif /* __AVX512BW__ */ diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index fb0aea70280..55a5d9fee9c 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512DQINTRIN_H_INCLUDED #define _AVX512DQINTRIN_H_INCLUDED -#ifndef __AVX512DQ__ +#if !defined (__AVX512DQ__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512dq") +#pragma GCC target("avx512dq,no-evex512") #define __DISABLE_AVX512DQ__ #endif /* __AVX512DQ__ */ diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index 90a00bec09a..d9b25e9287d 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512FINTRIN_H_INCLUDED #define _AVX512FINTRIN_H_INCLUDED -#ifndef __AVX512F__ +#if !defined (__AVX512F__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512f") +#pragma GCC target("avx512f,no-evex512") #define __DISABLE_AVX512F__ #endif /* __AVX512F__ */ diff --git a/gcc/config/i386/avx512fp16intrin.h b/gcc/config/i386/avx512fp16intrin.h index 12fcd64d7d6..aa708f9f5d0 100644 --- a/gcc/config/i386/avx512fp16intrin.h +++ b/gcc/config/i386/avx512fp16intrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512FP16INTRIN_H_INCLUDED #define _AVX512FP16INTRIN_H_INCLUDED -#ifndef __AVX512FP16__ +#if !defined (__AVX512FP16__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512fp16") +#pragma GCC target("avx512fp16,no-evex512") #define __DISABLE_AVX512FP16__ #endif /* __AVX512FP16__ */ diff --git a/gcc/config/i386/avx512fp16vlintrin.h b/gcc/config/i386/avx512fp16vlintrin.h index 64c52a25d8d..53449486b39 100644 --- a/gcc/config/i386/avx512fp16vlintrin.h +++ b/gcc/config/i386/avx512fp16vlintrin.h @@ -28,9 +28,9 @@ #ifndef __AVX512FP16VLINTRIN_H_INCLUDED #define __AVX512FP16VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512FP16__) +#if !defined(__AVX512VL__) || !defined(__AVX512FP16__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512fp16,avx512vl") +#pragma GCC target("avx512fp16,avx512vl,no-evex512") #define __DISABLE_AVX512FP16VL__ #endif /* __AVX512FP16VL__ */ diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h index cac55fe5e88..4ecc53b2bdd 100644 --- a/gcc/config/i386/avx512ifmavlintrin.h +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512IFMAVLINTRIN_H_INCLUDED #define _AVX512IFMAVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512IFMA__) +#if !defined(__AVX512VL__) || !defined(__AVX512IFMA__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512ifma,avx512vl") +#pragma GCC target("avx512ifma,avx512vl,no-evex512") #define __DISABLE_AVX512IFMAVL__ #endif /* __AVX512IFMAVL__ */ diff --git a/gcc/config/i386/avx512vbmi2vlintrin.h b/gcc/config/i386/avx512vbmi2vlintrin.h index 4424adc774e..31c23fdb68c 100644 --- a/gcc/config/i386/avx512vbmi2vlintrin.h +++ b/gcc/config/i386/avx512vbmi2vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VBMI2VLINTRIN_H_INCLUDED #define _AVX512VBMI2VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__) +#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vbmi2,avx512vl") +#pragma GCC target("avx512vbmi2,avx512vl,no-evex512") #define __DISABLE_AVX512VBMI2VL__ #endif /* __AVX512VBMIVL__ */ diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h index acec23b742f..909706f0dbe 100644 --- a/gcc/config/i386/avx512vbmivlintrin.h +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VBMIVLINTRIN_H_INCLUDED #define _AVX512VBMIVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VBMI__) +#if !defined(__AVX512VL__) || !defined(__AVX512VBMI__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vbmi,avx512vl") +#pragma GCC target("avx512vbmi,avx512vl,no-evex512") #define __DISABLE_AVX512VBMIVL__ #endif /* __AVX512VBMIVL__ */ diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h index 970dffc4bfe..2ed4d564d58 100644 --- a/gcc/config/i386/avx512vlbwintrin.h +++ b/gcc/config/i386/avx512vlbwintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLBWINTRIN_H_INCLUDED #define _AVX512VLBWINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512BW__) +#if !defined(__AVX512VL__) || !defined(__AVX512BW__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512bw") +#pragma GCC target("avx512vl,avx512bw,no-evex512") #define __DISABLE_AVX512VLBW__ #endif /* __AVX512VLBW__ */ diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index 1949737fe9c..95f6da36f99 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLDQINTRIN_H_INCLUDED #define _AVX512VLDQINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512DQ__) +#if !defined(__AVX512VL__) || !defined(__AVX512DQ__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512dq") +#pragma GCC target("avx512vl,avx512dq,no-evex512") #define __DISABLE_AVX512VLDQ__ #endif /* __AVX512VLDQ__ */ diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h index d4932f29b56..7f4e83a4367 100644 --- a/gcc/config/i386/avx512vlintrin.h +++ b/gcc/config/i386/avx512vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLINTRIN_H_INCLUDED #define _AVX512VLINTRIN_H_INCLUDED -#ifndef __AVX512VL__ +#if !defined (__AVX512VL__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vl") +#pragma GCC target("avx512vl,no-evex512") #define __DISABLE_AVX512VL__ #endif /* __AVX512VL__ */ @@ -13650,7 +13650,7 @@ _mm256_permutex_pd (__m256d __X, const int __M) #if !defined (__AVX512CD__) || !defined (__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512cd") +#pragma GCC target("avx512vl,avx512cd,no-evex512") #define __DISABLE_AVX512VLCD__ #endif diff --git a/gcc/config/i386/avx512vnnivlintrin.h b/gcc/config/i386/avx512vnnivlintrin.h index c62a6e82070..6c65a70f61c 100644 --- a/gcc/config/i386/avx512vnnivlintrin.h +++ b/gcc/config/i386/avx512vnnivlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VNNIVLINTRIN_H_INCLUDED #define _AVX512VNNIVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VNNI__) +#if !defined(__AVX512VL__) || !defined(__AVX512VNNI__) || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vnni,avx512vl") +#pragma GCC target("avx512vnni,avx512vl,no-evex512") #define __DISABLE_AVX512VNNIVL__ #endif /* __AVX512VNNIVL__ */ diff --git a/gcc/config/i386/avx512vp2intersectvlintrin.h b/gcc/config/i386/avx512vp2intersectvlintrin.h index ce68aee71ca..cad9b07a202 100644 --- a/gcc/config/i386/avx512vp2intersectvlintrin.h +++ b/gcc/config/i386/avx512vp2intersectvlintrin.h @@ -28,9 +28,10 @@ #ifndef _AVX512VP2INTERSECTVLINTRIN_H_INCLUDED #define _AVX512VP2INTERSECTVLINTRIN_H_INCLUDED -#if !defined(__AVX512VP2INTERSECT__) || !defined(__AVX512VL__) +#if !defined(__AVX512VP2INTERSECT__) || !defined(__AVX512VL__) \ + || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vp2intersect,avx512vl") +#pragma GCC target("avx512vp2intersect,avx512vl,no-evex512") #define __DISABLE_AVX512VP2INTERSECTVL__ #endif /* __AVX512VP2INTERSECTVL__ */ diff --git a/gcc/config/i386/avx512vpopcntdqvlintrin.h b/gcc/config/i386/avx512vpopcntdqvlintrin.h index df487a269de..19b3200b85d 100644 --- a/gcc/config/i386/avx512vpopcntdqvlintrin.h +++ b/gcc/config/i386/avx512vpopcntdqvlintrin.h @@ -28,9 +28,10 @@ #ifndef _AVX512VPOPCNTDQVLINTRIN_H_INCLUDED #define _AVX512VPOPCNTDQVLINTRIN_H_INCLUDED -#if !defined(__AVX512VPOPCNTDQ__) || !defined(__AVX512VL__) +#if !defined(__AVX512VPOPCNTDQ__) || !defined(__AVX512VL__) \ + || defined (__EVEX512__) #pragma GCC push_options -#pragma GCC target("avx512vpopcntdq,avx512vl") +#pragma GCC target("avx512vpopcntdq,avx512vl,no-evex512") #define __DISABLE_AVX512VPOPCNTDQVL__ #endif /* __AVX512VPOPCNTDQVL__ */ diff --git a/gcc/testsuite/gcc.target/i386/pr111889.c b/gcc/testsuite/gcc.target/i386/pr111889.c new file mode 100644 index 00000000000..4f7682a28b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr111889.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +#include + +__attribute__ ((target ("no-evex512,avx512vl"))) +__m256d foo (__m256d __W, __mmask8 __U, __m256d __A) +{ + return _mm256_mask_mov_pd (__W, __U, __A); +}