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[8.43.85.97]) by mx.google.com with ESMTPS id 28-20020a05620a049c00b007757f6ff384si98498qkr.610.2023.10.26.15.29.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 15:29:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7E5D73858281 for ; Thu, 26 Oct 2023 22:29:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id D2F5E3858D32 for ; Thu, 26 Oct 2023 22:29:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D2F5E3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D2F5E3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698359349; cv=none; b=RssEcA7TnilDrWqk7mxVQMPppOfsEC6m9JZm19qXeZT5jwbYsWO7w5aXANoLiT6BJZsmgfFs1A5tHP5bIam22GvnUmSqs9KuisN50+mHvT/Od/Je+2reyhHcEq9XlRjnyayaZ/R6xMKENon7YAUBnFoeB4LWgJTtH4+f1o+yLWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698359349; c=relaxed/simple; bh=JjfJHv9to5RBnhUQz/1/kDFryMPFbPjQsn8hHK2snTo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=A9xDr6P8QriGJ4EuCF8I8dZy1hlZ+M45ke4enVeRkI4BJl4xp8uKyd1Ik9BAIS9MqRl4lviGH24iowcnBjbbozpkMclR1NmPQTcTH3Qv6D4Rjupz9MCCN71GHb+4ftoJhnzE9Tvo4F8jrwqS0gDuED8icG4s6iNVybjwZyG6xAU= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp90t1698359339t187mfvl Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 27 Oct 2023 06:28:58 +0800 (CST) X-QQ-SSF: 01400000002000G0V000B00A0000000 X-QQ-FEAT: D6RqbDSxuq543PiEPLKxQNr0vXK4X0mioFFlBirignFioRWX70gozT0Vsl+2c Dxr2hVGpV6qHkVjOz2MDOOezqY1G7pSfm0Sjvli7vkwDqqAnpQt+PDm8GVP1EyF7s/N3qxT fcVvRxtqiCNVMeajdFrn960cjQEgxkTEDRc5gYAI7c1JsiV1fenCi4hUuTUvyiIjJnFrjuT VNVgSbj/dZF2TShkFXjLXurwMeUcNUhCHL8KeFYTrZiT/6o44brvFXMYEKh7/4a37nkPjth BkAZYJeo+Atx8j9cbIOj798NY+XxFGM+kdYBIG9PdzDRVhaAIfGXaXy1G7Vva2jYmzT/0LQ aLzo30W+SFoVSEHXF2rs8Ot/6G+3phyUYQkwg87hx4P/JeCGSY9TiZXEkO54w== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17564118351896009083 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [NFC] RISC-V: Move lmul calculation into macro Date: Fri, 27 Oct 2023 06:28:56 +0800 Message-Id: <20231026222856.123102-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780858877276972413 X-GMAIL-MSGID: 1780858877276972413 Notice we calculate LMUL according to --param=riscv-autovec-lmul in multiple places: int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; Create a new macro for it for easier matain. gcc/ChangeLog: * config/riscv/riscv-opts.h (TARGET_MAX_LMUL): New macro. * config/riscv/riscv-v.cc (preferred_simd_mode): Adapt macro. (autovectorize_vector_modes): Ditto. (can_find_related_mode_p): Ditto. --- gcc/config/riscv/riscv-opts.h | 4 ++++ gcc/config/riscv/riscv-v.cc | 17 +++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index e557f70f414..532b1b6b84a 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -121,4 +121,8 @@ enum riscv_entity /* TODO: Enable RVV movmisalign by default for now. */ #define TARGET_VECTOR_MISALIGN_SUPPORTED 1 +/* The maximmum LMUL according to user configuration. */ +#define TARGET_MAX_LMUL \ + (int) (riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 3fe8125801b..c79ec8ef32b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2228,16 +2228,15 @@ preferred_simd_mode (scalar_mode mode) vectorizer when we enable them in this target hook. Currently, we can support auto-vectorization in -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or -march=rv32_zve32x_zvl64b are disabled. */ - int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (autovec_use_vlmax_p ()) { - if (TARGET_MIN_VLEN < 128 && lmul < RVV_M2) + if (TARGET_MIN_VLEN < 128 && TARGET_MAX_LMUL < RVV_M2) return word_mode; /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and riscv_autovec_lmul as multiply factor to calculate the the NUNITS to get the auto-vectorization mode. */ poly_uint64 nunits; - poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * lmul; + poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL; poly_uint64 scalar_size = GET_MODE_SIZE (mode); gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); machine_mode rvv_mode; @@ -2417,10 +2416,9 @@ get_cmp_insn_code (rtx_code code, machine_mode mode) unsigned int autovectorize_vector_modes (vector_modes *modes, bool) { - int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (autovec_use_vlmax_p ()) { - poly_uint64 full_size = BYTES_PER_RISCV_VECTOR * lmul; + poly_uint64 full_size = BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL; /* Start with a RVVQImode where LMUL is the number of units that fit a whole vector. @@ -2448,7 +2446,7 @@ autovectorize_vector_modes (vector_modes *modes, bool) } /* Push all VLSmodes according to TARGET_MIN_VLEN. */ unsigned int i = 0; - unsigned int base_size = TARGET_MIN_VLEN * lmul / 8; + unsigned int base_size = TARGET_MIN_VLEN * TARGET_MAX_LMUL / 8; unsigned int size = base_size; machine_mode mode; while (size > 0 && get_vector_mode (QImode, size).exists (&mode)) @@ -2470,14 +2468,13 @@ can_find_related_mode_p (machine_mode vector_mode, scalar_mode element_mode, { if (!autovec_use_vlmax_p ()) return false; - int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (riscv_v_ext_vector_mode_p (vector_mode) - && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, + && multiple_p (BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL, GET_MODE_SIZE (element_mode), nunits)) return true; if (riscv_v_ext_vls_mode_p (vector_mode) - && multiple_p (TARGET_MIN_VLEN * lmul, GET_MODE_SIZE (element_mode), - nunits)) + && multiple_p (TARGET_MIN_VLEN * TARGET_MAX_LMUL, + GET_MODE_SIZE (element_mode), nunits)) return true; return false; }