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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s18-20020a05620a16b200b007758e5dba33si9675827qkj.469.2023.10.26.11.51.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 11:51:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BB69D3858D32 for ; Thu, 26 Oct 2023 18:51:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id CA5AB3858D32 for ; Thu, 26 Oct 2023 18:51:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CA5AB3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CA5AB3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698346264; cv=none; b=vpLABqv9GSOvQLzViy1zf5iEv6TPM0r+35/jjmny1YVD+guzt20ojMsLHojpncUKR18j709L2gwZj5qlYYRhEgpRJIit4LqTov55F4Qhsa2NSHB6vGXxD8cJJeBYmk6wy8CoEc+KeUxr9EiSoA0iMZfgjSbxtHRxy6SGn+x4gGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698346264; c=relaxed/simple; bh=DQinhlN5An+wnG5LdyCXqSV2NSuvNyXF7U6CtDoqY2w=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=dJbvDnn/d6GheTRuPz34iU6ypp/NACw8CpeX8selG0njKIa2U2uvcGGi34r4bBAaSPKeJtKJ78bGSB+CtfYoDTHudSRdLinubMwBwM7zaFecn6/IlpZAzsXkE8ZhZPyz26AdultcFKYRll81+Y/8ds8NkGq/jArzDySXw0vJXMU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from cyy-pc.lan (unknown [222.178.10.212]) by APP-05 (Coremail) with SMTP id zQCowAA3EJf8tDplvXb4AA--.57687S2; Fri, 27 Oct 2023 02:50:53 +0800 (CST) From: Yangyu Chen To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, andrew@sifive.com, jim.wilson.gcc@gmail.com, Yangyu Chen Subject: [PATCH] RISC-V: Fix wrong tune parameters on int_div Date: Fri, 27 Oct 2023 02:50:21 +0800 Message-ID: <20231026185021.654679-1-chenyangyu@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-CM-TRANSID: zQCowAA3EJf8tDplvXb4AA--.57687S2 X-Coremail-Antispam: 1UD129KBjvJXoWxGF4rWFWDtw17Cr18XFW3GFg_yoW5Kr1kp3 WrGry7C3s8uwsrurW8KayDWw43X3WDAF9xGryxWr4xXws5t3yUt3Zrtr4rG3s8urn7Ar13 ZF45WF1jkasrZrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48J MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AK xVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU5WlkUUUUU X-Originating-IP: [222.178.10.212] X-CM-SenderInfo: xfkh055dqj53w6lv2u4olvutnvoduhdfq/ X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780845158419891763 X-GMAIL-MSGID: 1780845158419891763 This patch fixes an issue with the cost on "int_div" in various RISC-V tune parameters including those for Rocket, SiFive U7 series, and T-Head C906. This incorrect cost value interferes with the optimization process. For example, it prevents the optimization of division by a constant to a more efficient method known as Barrett reduction. This lack of optimization negatively affects the performance of these systems. The integer div cost of the Rocket and SiFive U7 is taken from the Rocket-Chip Divider source code[1] with BigCore configuration[2]. It shows the divUnroll unchanged which is 1 by default. Thus, the maximum int_div cycles should be the dataWidth + 1, which is 33 for 32-bit and 65 for 64-bit. As for C906, the divider takes 2 cycle to start[3], and it produce 2-bit result each cycle[4]. Thus, the maximum int_div cycles should be the dataWidth / 2 + 2, which is 18 for 32-bit and 34 for 64-bit. I also test the performance on VisionFive2 which has Qual-Core Sifive U74. I write a simple C program to do 1e8 times div by constant 6 in int32. The result shows it takes 1.998s using div, and 0.420s using barrett reduction to replace div with mul, which is 4.75x faster. [1] https://github.com/chipsalliance/rocket-chip/blob/v1.6/src/main/scala/rocket/Multiplier.scala#L40 [2] https://github.com/chipsalliance/rocket-chip/blob/v1.6/src/main/scala/subsystem/Configs.scala#L97 [3] https://github.com/T-head-Semi/openc906/blob/af5614d72de7e5a4b8609c427d2e20af1deb21c4/C906_RTL_FACTORY/gen_rtl/iu/rtl/aq_iu_div.v#L267 [4] https://github.com/T-head-Semi/openc906/blob/af5614d72de7e5a4b8609c427d2e20af1deb21c4/C906_RTL_FACTORY/gen_rtl/iu/rtl/aq_iu_div_shift2_kernel.v#L93 gcc/ChangeLog: * config/riscv/riscv.cc: Fix wrong tune parameters on int_div Signed-off-by: Yangyu Chen --- gcc/config/riscv/riscv.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f2dcb0db6fb..ca9a2ca81d5 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -346,7 +346,7 @@ static const struct riscv_tune_param rocket_tune_info = { {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ - {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + {COSTS_N_INSNS (33), COSTS_N_INSNS (65)}, /* int_div */ 1, /* issue_rate */ 3, /* branch_cost */ 5, /* memory_cost */ @@ -361,7 +361,7 @@ static const struct riscv_tune_param sifive_7_tune_info = { {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ - {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + {COSTS_N_INSNS (33), COSTS_N_INSNS (65)}, /* int_div */ 2, /* issue_rate */ 4, /* branch_cost */ 3, /* memory_cost */ @@ -376,7 +376,7 @@ static const struct riscv_tune_param thead_c906_tune_info = { {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ - {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + {COSTS_N_INSNS (18), COSTS_N_INSNS (34)}, /* int_div */ 1, /* issue_rate */ 3, /* branch_cost */ 5, /* memory_cost */