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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id a18-20020a05620a02f200b00778910b49cesi7878041qko.528.2023.10.25.02.03.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 02:03:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B18B13857803 for ; Wed, 25 Oct 2023 09:03:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 2AD283857017 for ; Wed, 25 Oct 2023 09:03:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2AD283857017 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2AD283857017 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.169.211.239 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698224609; cv=none; b=YBGq5dulbvINVg9Smn2pBX9eBQgwTigKX6qyZW6gXQhRRWseWM2BHmBQ5iBJVaNVz+26YHXIaks12VD80DhqD8kfuiKI8+c7jMcNsaV//YZKkqJtCz5oJviSUIl2gvluPKK5oApnaR+eQeCopZenr8t5+GZL9bNHuyKt0h6qA1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698224609; c=relaxed/simple; bh=QduBOHE1CC3Pc+XFDkHvTDQOmpvGNkTRDtr6xEWwPvA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=eoeson5dyO0u8pR5ygxGuMzRiGgHWLHgqJ3tAuoT4lt+TA7+Xwpm5CK96v1Wktv61ZyfQMIL+lT+jGXMVR88DkkwV2/pgALmfFLR4nfIW02m2UnkFLwvtsBx+7m+yCHPhuPlvLe/ZboZfH1C6DfMgezl95zyu32Mv0ZKCHqY61I= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp72t1698224600twp7mhwy Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 25 Oct 2023 17:03:19 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 1VT9TMQFSYvY/BTFoJFu/AB+wKd+PGQwjj9gydJJMCUz7IxC3VGSVooKLFH8V ZraD4LbMefwguKrIwTdjxKfHry0ILK8MloocdBUlp0nNym5TIUDvOtNsBhIVp/d2mSCW3aH q3SLS1WaKgwrV6IXK8Cndwg2jo5ushk0/Ceu23tJjLgLNS3pIJ7Z2HQDvfRzkkWqF4i2Q3h 60nZAo0Llz6sIFgol0Zvv2laRAmxBNXtApO7JZtponZpI4n8wcNcNlUP5yJCkv618QTpz9E tyG523DUVL9RYgph07foD3zDAWEvpHdE10g2s+IANjSQpad+FUF4oxQsGuE2ArSTAeoicTo xrn8iC14nmDdM/Sb2OCf51z2ZIC1ngfA6/irogwSEqNiU/2y3Q41B/9Afl5eqjrYEhTr26a 2eITHC82kYY= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7486593945413230713 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v Date: Wed, 25 Oct 2023 17:03:17 +0800 Message-Id: <20231025090317.1458990-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780717592887939672 X-GMAIL-MSGID: 1780717592887939672 Address kito's comments of AVL propagation patch. Export the functions that are not only used by VSETVL PASS but also AVL propagation PASS. No functionality change. gcc/ChangeLog: * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v (tail_agnostic_p): Ditto. (validate_change_or_fail): Ditto. (nonvlmax_avl_type_p): Ditto. (vlmax_avl_p): Ditto. (get_sew): Ditto. (enum vlmul_type): Ditto. (count_regno_occurrences): Ditto. * config/riscv/riscv-v.cc (has_vl_op): Ditto. (get_default_ta): Ditto. (tail_agnostic_p): Ditto. (validate_change_or_fail): Ditto. (nonvlmax_avl_type_p): Ditto. (vlmax_avl_p): Ditto. (get_sew): Ditto. (enum vlmul_type): Ditto. (get_vlmul): Ditto. (count_regno_occurrences): Ditto. * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto. (has_vl_op): Ditto. (get_sew): Ditto. (get_vlmul): Ditto. (get_default_ta): Ditto. (tail_agnostic_p): Ditto. (count_regno_occurrences): Ditto. (validate_change_or_fail): Ditto. --- gcc/config/riscv/riscv-protos.h | 8 +++ gcc/config/riscv/riscv-v.cc | 83 ++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-vsetvl.cc | 70 --------------------------- 3 files changed, 91 insertions(+), 70 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index fffd9cd0b8a..668d75043ca 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -560,6 +560,14 @@ bool cmp_lmul_gt_one (machine_mode); bool gather_scatter_valid_offset_mode_p (machine_mode); bool vls_mode_valid_p (machine_mode); bool vlmax_avl_type_p (rtx_insn *); +bool has_vl_op (rtx_insn *); +bool tail_agnostic_p (rtx_insn *); +void validate_change_or_fail (rtx, rtx *, rtx, bool); +bool nonvlmax_avl_type_p (rtx_insn *); +bool vlmax_avl_p (rtx); +uint8_t get_sew (rtx_insn *); +enum vlmul_type get_vlmul (rtx_insn *); +int count_regno_occurrences (rtx_insn *, unsigned int); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d439ec06af0..3fe8125801b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4447,4 +4447,87 @@ vlmax_avl_type_p (rtx_insn *rinsn) return INTVAL (avl_type) == VLMAX; } +/* Return true if it is an RVV instruction depends on VL global + status register. */ +bool +has_vl_op (rtx_insn *rinsn) +{ + return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn); +} + +/* Get default tail policy. */ +static bool +get_default_ta () +{ + /* For the instruction that doesn't require TA, we still need a default value + to emit vsetvl. We pick up the default value according to prefer policy. */ + return (bool) (get_prefer_tail_policy () & 0x1 + || (get_prefer_tail_policy () >> 1 & 0x1)); +} + +/* Helper function to get TA operand. */ +bool +tail_agnostic_p (rtx_insn *rinsn) +{ + /* If it doesn't have TA, we return agnostic by default. */ + extract_insn_cached (rinsn); + int ta = get_attr_ta (rinsn); + return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta); +} + +/* Change insn and Assert the change always happens. */ +void +validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group) +{ + bool change_p = validate_change (object, loc, new_rtx, in_group); + gcc_assert (change_p); +} + +/* Return true if it is NONVLMAX AVL TYPE. */ +bool +nonvlmax_avl_type_p (rtx_insn *rinsn) +{ + extract_insn_cached (rinsn); + int index = get_attr_avl_type_idx (rinsn); + if (index == INVALID_ATTRIBUTE) + return false; + rtx avl_type = recog_data.operand[index]; + return INTVAL (avl_type) == NONVLMAX; +} + +/* Return true if RTX is RVV VLMAX AVL. */ +bool +vlmax_avl_p (rtx x) +{ + return x && rtx_equal_p (x, RVV_VLMAX); +} + +/* Helper function to get SEW operand. We always have SEW value for + all RVV instructions that have VTYPE OP. */ +uint8_t +get_sew (rtx_insn *rinsn) +{ + return get_attr_sew (rinsn); +} + +/* Helper function to get VLMUL operand. We always have VLMUL value for + all RVV instructions that have VTYPE OP. */ +enum vlmul_type +get_vlmul (rtx_insn *rinsn) +{ + return (enum vlmul_type) get_attr_vlmul (rinsn); +} + +/* Count the number of REGNO in RINSN. */ +int +count_regno_occurrences (rtx_insn *rinsn, unsigned int regno) +{ + int count = 0; + extract_insn (rinsn); + for (int i = 0; i < recog_data.n_operands; i++) + if (refers_to_regno_p (regno, recog_data.operand[i])) + count++; + return count; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 73a6d4b7406..77dbf159d41 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -255,12 +255,6 @@ policy_to_str (bool agnostic_p) return agnostic_p ? "agnostic" : "undisturbed"; } -static bool -vlmax_avl_p (rtx x) -{ - return x && rtx_equal_p (x, RVV_VLMAX); -} - /* Return true if it is an RVV instruction depends on VTYPE global status register. */ static bool @@ -269,14 +263,6 @@ has_vtype_op (rtx_insn *rinsn) return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn); } -/* Return true if it is an RVV instruction depends on VL global - status register. */ -static bool -has_vl_op (rtx_insn *rinsn) -{ - return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn); -} - /* Return true if the instruction ignores VLMUL field of VTYPE. */ static bool ignore_vlmul_insn_p (rtx_insn *rinsn) @@ -371,32 +357,6 @@ get_avl (rtx_insn *rinsn) return recog_data.operand[get_attr_vl_op_idx (rinsn)]; } -/* Helper function to get SEW operand. We always have SEW value for - all RVV instructions that have VTYPE OP. */ -static uint8_t -get_sew (rtx_insn *rinsn) -{ - return get_attr_sew (rinsn); -} - -/* Helper function to get VLMUL operand. We always have VLMUL value for - all RVV instructions that have VTYPE OP. */ -static enum vlmul_type -get_vlmul (rtx_insn *rinsn) -{ - return (enum vlmul_type) get_attr_vlmul (rinsn); -} - -/* Get default tail policy. */ -static bool -get_default_ta () -{ - /* For the instruction that doesn't require TA, we still need a default value - to emit vsetvl. We pick up the default value according to prefer policy. */ - return (bool) (get_prefer_tail_policy () & 0x1 - || (get_prefer_tail_policy () >> 1 & 0x1)); -} - /* Get default mask policy. */ static bool get_default_ma () @@ -407,16 +367,6 @@ get_default_ma () || (get_prefer_mask_policy () >> 1 & 0x1)); } -/* Helper function to get TA operand. */ -static bool -tail_agnostic_p (rtx_insn *rinsn) -{ - /* If it doesn't have TA, we return agnostic by default. */ - extract_insn_cached (rinsn); - int ta = get_attr_ta (rinsn); - return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta); -} - /* Helper function to get MA operand. */ static bool mask_agnostic_p (rtx_insn *rinsn) @@ -476,18 +426,6 @@ get_max_float_sew () gcc_unreachable (); } -/* Count the number of REGNO in RINSN. */ -static int -count_regno_occurrences (rtx_insn *rinsn, unsigned int regno) -{ - int count = 0; - extract_insn (rinsn); - for (int i = 0; i < recog_data.n_operands; i++) - if (refers_to_regno_p (regno, recog_data.operand[i])) - count++; - return count; -} - enum def_type { REAL_SET = 1 << 0, @@ -696,14 +634,6 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int regno) return true; } -/* Change insn and Assert the change always happens. */ -static void -validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group) -{ - bool change_p = validate_change (object, loc, new_rtx, in_group); - gcc_assert (change_p); -} - /* This flags indicates the minimum demand of the vl and vtype values by the RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV instruction only needs the SEW/LMUL ratio to remain the same, and does not