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[8.43.85.97]) by mx.google.com with ESMTPS id s7-20020a05620a254700b00770f0ba76adsi7252833qko.678.2023.10.24.03.51.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 03:51:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55369385C6F6 for ; Tue, 24 Oct 2023 10:51:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id CA62B3858C01 for ; Tue, 24 Oct 2023 10:50:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CA62B3858C01 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CA62B3858C01 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698144637; cv=none; b=bCbWRmipTyExgFQCFvi2U73m02PbFCfFY5ac+amgOKPKzm0B+08tEf9yFiR/fmYnioIbTnKMkskLPWluuNZP91TokUorFbbDn4bQ1DBtUPLNHs61cPhAAsjgcPO7THlH9/IUeg20/rJuNDyiGmqXtFj9E50sh2n0mGFO8/YEWWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698144637; c=relaxed/simple; bh=mb1EYMRxu22yqkwvCDEm0ojgDDWcRu9ZS2Nc97utHik=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=mJGEGl3XdLhpvpj8n2Y2k7Xavck/TSavrgcjbLuesNp2wkyaT1O37l6LMTytRDRqe/NZZaEat7DrBRbc8uZitSUfGWzbx7qrgT22BihwxitE3HGFKn/MjcaGtGaDi7pZV+MF4/2eziBKkbsHnTY7Nl0IkX8PPdiRXa6IqcGdmHU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FE36C15; Tue, 24 Oct 2023 03:51:12 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1248B3F64C; Tue, 24 Oct 2023 03:50:30 -0700 (PDT) From: Richard Sandiford To: jlaw@ventanamicro.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 1/6] rtl-ssa: Ensure global registers are live on exit Date: Tue, 24 Oct 2023 11:50:01 +0100 Message-Id: <20231024105006.3337671-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231024105006.3337671-1-richard.sandiford@arm.com> References: <20231024105006.3337671-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-24.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780633740749000799 X-GMAIL-MSGID: 1780633740749000799 RTL-SSA mostly relies on DF for block-level register liveness information, including artificial uses and defs at the beginning and end of blocks. But one case was missing. DF does not add artificial uses of global registers to the beginning or end of a block. Instead it marks them as used within every block when computing LR and LIVE problems. For RTL-SSA, global registers behave like memory, which in turn behaves like gimple vops. We need to ensure that they are live on exit so that final definitions do not appear to be unused. Also, the previous live-on-exit handling only considered the exit block itself. It needs to consider non-local gotos as well, since they jump directly to some code in a parent function and so do not have a path to the exit block. gcc/ * rtl-ssa/blocks.cc (function_info::add_artificial_accesses): Force global registers to be live on exit. Handle any block with zero successors like an exit block. --- gcc/rtl-ssa/blocks.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/gcc/rtl-ssa/blocks.cc b/gcc/rtl-ssa/blocks.cc index ecce7a68c59..49c0d15b3cf 100644 --- a/gcc/rtl-ssa/blocks.cc +++ b/gcc/rtl-ssa/blocks.cc @@ -866,11 +866,14 @@ function_info::add_artificial_accesses (build_info &bi, df_ref_flags flags) start_insn_accesses (); + HARD_REG_SET added_regs = {}; FOR_EACH_ARTIFICIAL_USE (ref, cfg_bb->index) if ((DF_REF_FLAGS (ref) & DF_REF_AT_TOP) == flags) { unsigned int regno = DF_REF_REGNO (ref); machine_mode mode = GET_MODE (DF_REF_REAL_REG (ref)); + if (HARD_REGISTER_NUM_P (regno)) + SET_HARD_REG_BIT (added_regs, regno); // A definition must be available. gcc_checking_assert (bitmap_bit_p (&lr_info->in, regno) @@ -879,10 +882,20 @@ function_info::add_artificial_accesses (build_info &bi, df_ref_flags flags) m_temp_uses.safe_push (create_reg_use (bi, insn, { mode, regno })); } - // Track the return value of memory by adding an artificial use of - // memory at the end of the exit block. - if (flags == 0 && cfg_bb->index == EXIT_BLOCK) + // Ensure that global registers and memory are live at the end of any + // block that has no successors, such as the exit block and non-local gotos. + // Global registers have to be singled out because they are not part of + // the DF artifical use list (they are instead treated as used within + // every block). + if (flags == 0 && EDGE_COUNT (cfg_bb->succs) == 0) { + for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; ++i) + if (global_regs[i] && !TEST_HARD_REG_BIT (added_regs, i)) + { + auto mode = reg_raw_mode[i]; + m_temp_uses.safe_push (create_reg_use (bi, insn, { mode, i })); + } + auto *use = allocate (insn, memory, bi.current_mem_value ()); add_use (use); m_temp_uses.safe_push (use);