diff mbox series

[Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947]

Message ID 20231024022139.218915-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Oct. 24, 2023, 2:21 a.m. UTC 
  ICE on vsetvli a5, 8 instruction demand info.

The AVL is const_int 8 which ICE on RENGO caller.

Committed as it is obvious fix.

	PR target/111947

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Add REGNO check.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr111947.c: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc                  | 15 +++++++++------
 .../gcc.target/riscv/rvv/vsetvl/pr111947.c        | 13 +++++++++++++
 2 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 5ef0f726e4a..f2f19e423bf 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2633,13 +2633,16 @@  pre_vsetvl::compute_lcm_local_properties ()
 	      if (!info.has_nonvlmax_reg_avl () && !info.has_vl ())
 		continue;
 
-	      unsigned int regno;
-	      sbitmap_iterator sbi;
-	      EXECUTE_IF_SET_IN_BITMAP (m_reg_def_loc[bb->index ()], 0, regno,
-					sbi)
+	      if (info.has_nonvlmax_reg_avl ())
 		{
-		  if (regno == REGNO (info.get_avl ()))
-		    bitmap_clear_bit (m_transp[bb->index ()], i);
+		  unsigned int regno;
+		  sbitmap_iterator sbi;
+		  EXECUTE_IF_SET_IN_BITMAP (m_reg_def_loc[bb->index ()], 0,
+					    regno, sbi)
+		    {
+		      if (regno == REGNO (info.get_avl ()))
+			bitmap_clear_bit (m_transp[bb->index ()], i);
+		    }
 		}
 
 	      for (const insn_info *insn : bb->real_nondebug_insns ())
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
new file mode 100644
index 00000000000..cea19b70e20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */
+
+char *a;
+b() {
+  int c[2];
+  int d = 0;
+  for (; d < 16; d += 2)
+    c[d / 2] = a[d | 1];
+  if (c[0])
+    for (;;)
+      ;
+}