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[8.43.85.97]) by mx.google.com with ESMTPS id e4-20020a056214162400b0065af751dbb1si5032215qvw.448.2023.10.23.00.54.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 00:54:08 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NoIoMVly; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3D6B33858439 for ; Mon, 23 Oct 2023 07:54:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 873003858CDA for ; Mon, 23 Oct 2023 07:53:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 873003858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 873003858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.136 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698047626; cv=none; b=kSEBQkKWketCmj9gdPBSFH7MRWXJ4TCpnCRgGfdyXjdRtkraKqQBJBPzvAZfXAqsxXnyD5682HEAJ6BX9iR9/KuwAWCIfo5eGM/Ue3SEPK02PzsacolCsJp1W7OHrxB4rDg1ikFE1k98ID5qCTqySopdeQ9coGCgMRZQ1NswWBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698047626; c=relaxed/simple; bh=mmLaAGia5ICNDXUXpHlN4MMw8HqPuTmYKk+RbWFFLFU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=v3on9aM7Gs8oAJ80lngUfv799V2lNnfV8lJn4oiMx4ydy1OkRA2Lxu10KOMa1nASzB1L1ofWWwTz202379A6SokbPFgC+uD0Qiw1yxHiwlHcZFTM3TYtDYUMtOSamjp8trt1XOvEbc8o7Bn6GK9X9PMHcDRO+icOJkPgUT1+xfU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698047625; x=1729583625; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=mmLaAGia5ICNDXUXpHlN4MMw8HqPuTmYKk+RbWFFLFU=; b=NoIoMVlyLUEpmfEMmkgcIOUBcOyFchMqOftu5dPnAfQl3LkrQq5+7v8/ aSutE2KJkCwTUtuC5bJrkbX4bDT5rsItpfRttwruhjEqgYo9FvxNzNP9Q Qh3IfRbJdJ7vnmALQdTYnOJUZ/LyTaxQl8VRpvSMLsTafB4WdP54hOn0H z8mmJsTy67A+IVDTeBVKJnSjTYqKm6No24gD3bBSmrBujR9Ue1xltOjwF MVbLq2ttiwZKRZjDJGOFC2KW//n2DsqjeUbxapz69rE+wIf2pvterwUoL a3EmX6kz82l1UUnzcPE515PeliAKcHJtVpWxZWi6lgtLfamAGeDs+Kh3T Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="366138358" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="366138358" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 00:53:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="931612915" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="931612915" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga005.jf.intel.com with ESMTP; 23 Oct 2023 00:53:41 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id C4ABA10057F8; Mon, 23 Oct 2023 15:53:40 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc Date: Mon, 23 Oct 2023 15:53:35 +0800 Message-Id: <20231023075335.3063731-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780532011199889579 X-GMAIL-MSGID: 1780532011199889579 From: Pan Li For trunc function autovec, there will be one step like below take MU for the merge operand. rtx tmp = gen_reg_rtx (vec_int_mode); emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); The MU will leave the tmp (aka dest register) register unmasked elements unchanged and it is undefined here. This patch would like to adjust the MU to MA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type arg. (expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 91ad6a61fa8..fb6a4e561db 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4144,12 +4144,20 @@ emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask, static void emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask, - machine_mode vec_mode) + insn_type type, machine_mode vec_mode) { - rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; insn_code icode = code_for_pred (FIX, vec_mode); - emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops); + if (type & USE_VUNDEF_MERGE_P) + { + rtx cvt_x_ops[] = {op_dest, mask, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } + else + { + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } } void @@ -4285,7 +4293,7 @@ expand_vec_trunc (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, rounding to zero (aka truncate). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); + emit_vec_cvt_x_f_rtz (tmp, op_1, mask, UNARY_OP_TAMA, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the rint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);