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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w15-20020ae9e50f000000b0077578612983si4627225qkf.6.2023.10.22.18.26.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 18:26:46 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=a9ygGVBc; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB6F93858C66 for ; Mon, 23 Oct 2023 01:26:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 769E73858D39 for ; Mon, 23 Oct 2023 01:26:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 769E73858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 769E73858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.136 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698024383; cv=none; b=IjpQ0wHbNtNbKh1faPgglOK72l1R1T+63iA5MuKLHn+LiyNyMdLeWipPa+k7UoKFcXFQFSqCuqXApaBoHNTTe+KTLLhlc222mztGpfIR8U4B/F6NceCqylOYvN0adIAHqFDpAzRBQS8Xz+6nKTKL+Av5FJiEQglc+vIjoJodSws= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698024383; c=relaxed/simple; bh=oyQXhBwYgCYhPboj8uF+XD9FkUWoMC0Iam5+zd2TH+c=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=gc4bH62SOy2u5yaAEsjUkJt8emmJqQqHOo3qL/rDPit2Y5TrDP+RWNR/B2VjRPc3kM5y2X272BfvmqgajiroOuDtARtp2sDriWQRe0HUPhh9PvtSsOyFVRqnZXaiOolCVXwsVB7+EU2egXHSdUF/qDBveYnUZsYo0YVzFqvW2u8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698024381; x=1729560381; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=oyQXhBwYgCYhPboj8uF+XD9FkUWoMC0Iam5+zd2TH+c=; b=a9ygGVBcES8997mSWlYPrwt6emOjQJ7+f0cOjNp6uwKRaxPShvMqZ1WJ Pls97LVr54LvTA5fAnrHWlnts7/2VhL6BbTX9BAGIBd5TryfFqxWAzsgM UsZaj95NlWG48zdNxg000fBsdwdf22yTtDIv0i4OGZo7xk7OiC5JVhDNH hrOfYseVdAnyCW7/xzaqNey+pQ9dSagFb1UWvsEW1JK0zE9aviyKsNI3R jDGR7RMyEHX2x9L4ShAw0zlg2Fhgf5UtOrjlFKviVtzdWO+BvB3sMK7N3 XQbwOwTGXAKLqyfWsbxK4XE4vSL5VMDyq89yr+9CvQZj1XQK/3zxVIMc5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="366095340" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="366095340" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2023 18:26:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="5634460" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa001.jf.intel.com with ESMTP; 22 Oct 2023 18:25:02 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A1AF1100571F; Mon, 23 Oct 2023 09:26:16 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register in math Date: Mon, 23 Oct 2023 09:26:14 +0800 Message-Id: <20231023012614.1420783-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780507639940506266 X-GMAIL-MSGID: 1780507639940506266 From: Pan Li For math function autovec, there will be one step like rtx tmp = gen_reg_rtx (vec_int_mode); emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); The MU will leave the tmp (aka dest register) register unmasked elements unchanged and it is undefined here. This patch would like to adjust the MU to MA. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum insn_type): Add new type values. * config/riscv/riscv-v.cc (emit_vec_cvt_x_f): Add undef merge operand handling. (expand_vec_ceil): Take MA instead of MU for tmp register. (expand_vec_floor): Ditto. (expand_vec_nearbyint): Ditto. (expand_vec_rint): Ditto. (expand_vec_round): Ditto. (expand_vec_roundeven): Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-protos.h | 5 +++++ gcc/config/riscv/riscv-v.cc | 24 ++++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f7a9a02f1f9..5dc97c2adc0 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -306,6 +306,11 @@ enum insn_type : unsigned int UNARY_OP_FRM_RMM = UNARY_OP | FRM_RMM_P, UNARY_OP_FRM_RUP = UNARY_OP | FRM_RUP_P, UNARY_OP_FRM_RDN = UNARY_OP | FRM_RDN_P, + UNARY_OP_TAMA_FRM_DYN = UNARY_OP_TAMA | FRM_DYN_P, + UNARY_OP_TAMA_FRM_RUP = UNARY_OP_TAMA | FRM_RUP_P, + UNARY_OP_TAMA_FRM_RDN = UNARY_OP_TAMA | FRM_RDN_P, + UNARY_OP_TAMA_FRM_RMM = UNARY_OP_TAMA | FRM_RMM_P, + UNARY_OP_TAMA_FRM_RNE = UNARY_OP_TAMA | FRM_RNE_P, UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P, UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P, UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P, diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 383af55fe3a..91ad6a61fa8 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4108,10 +4108,18 @@ static void emit_vec_cvt_x_f (rtx op_dest, rtx op_src, rtx mask, insn_type type, machine_mode vec_mode) { - rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; insn_code icode = code_for_pred_fcvt_x_f (UNSPEC_VFCVT, vec_mode); - emit_vlmax_insn (icode, type, cvt_x_ops); + if (type & USE_VUNDEF_MERGE_P) + { + rtx cvt_x_ops[] = {op_dest, mask, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } + else + { + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } } static void @@ -4157,7 +4165,7 @@ expand_vec_ceil (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, with rounding up (aka ceil). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RUP, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_RUP, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the final result. To avoid unnecessary frm register access, we use RUP here and it will @@ -4182,7 +4190,7 @@ expand_vec_floor (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, with rounding down (aka floor). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RDN, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_RDN, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the floor result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RDN, vec_fp_mode); @@ -4208,7 +4216,7 @@ expand_vec_nearbyint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-4: Convert to integer on mask, with rounding down (aka nearbyint). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_DYN, vec_fp_mode); /* Step-5: Convert to floating-point on mask for the nearbyint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); @@ -4233,7 +4241,7 @@ expand_vec_rint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, with dyn rounding (aka rint). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_DYN, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the rint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); @@ -4255,7 +4263,7 @@ expand_vec_round (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, rounding to nearest (aka round). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RMM, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_RMM, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the round result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RMM, vec_fp_mode); @@ -4299,7 +4307,7 @@ expand_vec_roundeven (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, rounding to nearest, ties to even. */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RNE, vec_fp_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMA_FRM_RNE, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the rint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RNE, vec_fp_mode);