From patchwork Fri Oct 20 09:53:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 155947 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp939879vqb; Fri, 20 Oct 2023 02:54:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHIeLoire8/rZFm6Ynm5jxS6tvB4cf8FSm1Q5FfS3qimyc2CEeg5lpCkPQVHUnpI9kfJUZX X-Received: by 2002:a05:620a:2845:b0:775:93aa:ce27 with SMTP id h5-20020a05620a284500b0077593aace27mr1378090qkp.3.1697795669565; Fri, 20 Oct 2023 02:54:29 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697795669; cv=pass; d=google.com; s=arc-20160816; b=Ljkw5EgfTq393XA/buAikWAXCBDdJa7/mJJ3SzDOaOS+Vilme6fCzbMOfyajMxTOsR zDoifznuimwxUZ5FeJDN+QZO/ecWqoifB8KEMukiVaHoCufCNUzwO8hQ42InghgRqUiG 6PBwKiYMySEtK/KkR8iDis44SyXv6ZMzoIPHhpGnxY9aGZKSWTWofST8fD/ZwpXtrzH1 9Iqsof2n7nvfb0ggOv53owY2dA1W/zaUHsRvNJr8mSq5w5GNVdXgEFPf1mwtYMwKVal0 CP8Go2gqGz+IZcknuR/uKqHEJZhgE0RTmDRM0oG953IfhkVVrYIeDT8GrH/QA5nCOD7U xTTw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=VMnJgJAvhFpfURy31o+JqILTcqgEE0dIyzFxMzCTRis=; fh=9oFhVPKihcNP6VY2Nsu6+FGvAEKY/HNABCPdk6S267g=; b=b89DZiEwY4C0g5xauwEcD866AVLZujlf84W2ifaymvDcrp+pcpDhnmW4RQc4Pwg3kd wvJczJ6QdZPAz1OX6BiI8o84tbz4abmvVTeLqP4wrMjrQUSK/r051m3TH2XJpGosGTu8 ujb0hnFE5JUe6AdGrblA190IQ/W5Yw2sCkCjiMNGMQvRGxJSLfVylTX/XMOXaqr3o648 G8RogGqCVF2h9S478JI+kryhon2II40+EqHj2zzpx8y17Mw3/AsfI8Irzns8VqnEMf7N +qcYyno9g7zjd/VBPXPibPtz2DD0UFABcdyzyEiBuj8eBEp5k6zjIGUDSwTd+3hg3Xr6 l6tw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=mleZ1vra; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id f34-20020a05622a1a2200b0041951625e0esi992585qtb.29.2023.10.20.02.54.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 02:54:29 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=mleZ1vra; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 54CB8385770A for ; Fri, 20 Oct 2023 09:54:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by sourceware.org (Postfix) with ESMTPS id BD74E3858D39 for ; Fri, 20 Oct 2023 09:53:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BD74E3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BD74E3858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697795643; cv=none; b=wqKQSOpFrYwZhLn6glnqoAGP9qWiAyvFVdlSMiSScaQCvdKx4JPomBu5Lj5BA5XlrZNPWW81OPKCgVymp4ilSdZfHeTat5N3fRaTC/PjJZyDga9yQHLuFhiqiM/tJPPgTIsMF8WKjOMXW7F2/Wx/xA1REmoU5IeehK31C4qb/Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697795643; c=relaxed/simple; bh=e+4QOULL7ACmYh1U4KLDc1ZkfMhHKc7ivQ+1SGzOuCs=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=NYISRJCGCmcjyd9u4GIjnYlBkhaNL1kky98lPPPZXO4jvCuZWFKaEVpps/fU4uR5g9sckfNhPT2uVOpHXlwJgntdRS6WaStUkyFDyT26vsXkbZK1EOYAU50tUzgvuw3YJpVaczu2SB4nddnLZecBrd+56ZwkkEudaswBhluGNZ0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-53e2dc8fa02so838502a12.2 for ; Fri, 20 Oct 2023 02:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1697795638; x=1698400438; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VMnJgJAvhFpfURy31o+JqILTcqgEE0dIyzFxMzCTRis=; b=mleZ1vrafsERKXHEIbJeEofx/eehVzbKexmpHbT5kJ1uyhw6hbrAS3HVohqtBXs5wO 2Vwj1xHbwFLADZx9q67mg7bkI/JihV3F9nOr0CqMRALAalfXRosTVFqhVbLMfmHOP6Ou FlRTogeo5eskVUZeKkbn5CNStUUb69qsWRrI5hJTMNl+TaA3Ym/lW6qo1gDeZRq49EBU Q1dE1dqzZYT7zCXmlIACWidJI2wgKU9Geu4nKJmgJfW4rmZApKTOZs9YjMyW48nRDf6K kGSEYZ3uE/wOCSGvVjNeKtyefW3SE1BGgY5Vk8G3boiPe/nYLam/Qnv9RbtemUr97eY/ Dj+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697795638; x=1698400438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VMnJgJAvhFpfURy31o+JqILTcqgEE0dIyzFxMzCTRis=; b=Whr65fhm3/I5thGp/tAeXss0eTtp1Wyl4TWXHCdODOc5hQY/AelOfuNJW8A6tU7RIC UuhCF/Fp9yGyo0B5UzLgZsh5ngVBMvJ4YbdVmxb3MsgvE8WFeKg9Pg2VTwxMLHY5Ab29 EnMYn87sCkYifbBg+73wCDI/DRjj6Diw21FWyZ/BpqDzx24//lKoGK4zvfQn2xpaE9X3 HY7ZBCaWwGuFu4093786Fn+cAzrkRu8TMyxuAAgVDZ15RaeVbCgYTWzLT4b+tJoqy14T e1hpdSwyYJi+jhdMGrBp7MSKxQWTQmKAAosPaH0kEArVSkoaFGsqY4hLqEVFRhYWRWk6 SY9w== X-Gm-Message-State: AOJu0YyVNuocAXCuu78xW8TkI6ZSf/ir8hkgX3sY+CBFqMms/+s07AZK mzhU0ZjI5uwwcFl6HhFTMRfiUo474k1S9GD5I7g= X-Received: by 2002:a50:d79b:0:b0:533:97c:8414 with SMTP id w27-20020a50d79b000000b00533097c8414mr1029326edi.7.1697795637727; Fri, 20 Oct 2023 02:53:57 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id w21-20020a50d795000000b0053e4d1cbc6esm1147688edi.55.2023.10.20.02.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 02:53:57 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v2 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension Date: Fri, 20 Oct 2023 11:53:48 +0200 Message-ID: <20231020095348.2455729-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020095348.2455729-1-christoph.muellner@vrull.eu> References: <20231020095348.2455729-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780267792354717725 X-GMAIL-MSGID: 1780267792354717725 From: Christoph Müllner The XTheadFMemIdx ISA extension provides additional load and store instructions for floating-point registers with new addressing modes. The following memory accesses types are supported: * load/store: [w,d] (single-precision FP, double-precision FP) The following addressing modes are supported: * register offset with additional immediate offset (4 instructions): flr, fsr * zero-extended register offset with additional immediate offset (4 instructions): flur, fsur These addressing modes are also part of the similar XTheadMemIdx ISA extension support, whose code is reused and extended to support floating-point registers. One challenge that this patch needs to solve are GP registers in FP-mode (e.g. "(reg:DF a2)"), which cannot be handled by the XTheadFMemIdx instructions. Such registers are the result of independent optimizations, which can happen after register allocation. This patch uses a simple but efficient method to address this: add a dependency for XTheadMemIdx to XTheadFMemIdx optimizations. This allows to use the instructions from XTheadMemIdx in case of such registers. The added tests ensure that this feature won't regress without notice. Testing: GCC regression test suite and SPEC CPU 2017 intrate (base&peak). Signed-off-by: Christoph Müllner gcc/ChangeLog: * config/riscv/riscv.cc (riscv_index_reg_class): Return GR_REGS for XTheadFMemIdx. (riscv_regno_ok_for_index_p): Add support for XTheadFMemIdx. * config/riscv/riscv.h (HARDFP_REG_P): New macro. * config/riscv/thead.cc (is_fmemidx_mode): New function. (th_memidx_classify_address_index): Add support for XTheadFMemIdx. (th_fmemidx_output_index): New function. (th_output_move): Add support for XTheadFMemIdx. * config/riscv/thead.md (TH_M_ANYF): New mode iterator. (TH_M_NOEXTF): Likewise. (*th_fmemidx_movsf_hardfloat): New INSN. (*th_fmemidx_movdf_hardfloat_rv64): Likewise. (*th_fmemidx_I_a): Likewise. (*th_fmemidx_I_c): Likewise. (*th_fmemidx_US_a): Likewise. (*th_fmemidx_US_c): Likewise. (*th_fmemidx_UZ_a): Likewise. (*th_fmemidx_UZ_c): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmemidx-index-update.c: New test. * gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test. * gcc.target/riscv/xtheadfmemidx-index.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex.c: New test. --- gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/riscv.h | 2 + gcc/config/riscv/thead.cc | 65 ++++++- gcc/config/riscv/thead.md | 161 ++++++++++++++++++ .../riscv/xtheadfmemidx-index-update.c | 20 +++ .../xtheadfmemidx-index-xtheadbb-update.c | 20 +++ .../riscv/xtheadfmemidx-index-xtheadbb.c | 22 +++ .../gcc.target/riscv/xtheadfmemidx-index.c | 22 +++ .../riscv/xtheadfmemidx-uindex-update.c | 20 +++ .../xtheadfmemidx-uindex-xtheadbb-update.c | 20 +++ .../riscv/xtheadfmemidx-uindex-xtheadbb.c | 24 +++ .../gcc.target/riscv/xtheadfmemidx-uindex.c | 25 +++ 12 files changed, 400 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 70aaaa53b76..2ecdd521b75 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1084,7 +1084,7 @@ riscv_regno_mode_ok_for_base_p (int regno, enum reg_class riscv_index_reg_class () { - if (TARGET_XTHEADMEMIDX) + if (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) return GR_REGS; return NO_REGS; @@ -1097,7 +1097,7 @@ riscv_index_reg_class () int riscv_regno_ok_for_index_p (int regno) { - if (TARGET_XTHEADMEMIDX) + if (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) return riscv_regno_mode_ok_for_base_p (regno, VOIDmode, 1); return 0; diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index eb162abcb92..1e9813b4f39 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -372,6 +372,8 @@ ASM_MISA_SPEC ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) #define FP_REG_P(REGNO) \ ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) +#define HARDFP_REG_P(REGNO) \ + ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST) #define V_REG_P(REGNO) \ ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM) #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 236b590fd80..ebad379dbc5 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -592,6 +592,18 @@ is_memidx_mode (machine_mode mode) return false; } +static bool +is_fmemidx_mode (machine_mode mode) +{ + if (mode == SFmode && TARGET_HARD_FLOAT) + return true; + + if (mode == DFmode && TARGET_DOUBLE_FLOAT) + return true; + + return false; +} + /* Return true if X is a valid address for T-Head's memory addressing modes with scaled register offsets for machine mode MODE. If it is, fill in INFO appropriately (if non-NULL). @@ -602,7 +614,8 @@ th_memidx_classify_address_index (struct riscv_address_info *info, rtx x, machine_mode mode, bool strict_p) { /* Ensure that the mode is supported. */ - if (!(TARGET_XTHEADMEMIDX && is_memidx_mode (mode))) + if (!(TARGET_XTHEADMEMIDX && is_memidx_mode (mode)) + && !(TARGET_XTHEADFMEMIDX && is_fmemidx_mode (mode))) return false; if (GET_CODE (x) != PLUS) @@ -755,6 +768,40 @@ th_memidx_output_index (rtx x, machine_mode mode, bool load) return buf; } +/* Provide a buffer for a th.flX/th.fluX/th.fsX/th.fsuX instruction + for the given MODE. If LOAD is true, a load instruction will be + provided (otherwise, a store instruction). If X is not suitable + return NULL. */ + +static const char * +th_fmemidx_output_index (rtx x, machine_mode mode, bool load) +{ + struct riscv_address_info info; + static char buf[128] = {0}; + + /* Validate x. */ + if (!th_memidx_classify_address_index (&info, x, mode, false)) + return NULL; + + int index = exact_log2 (GET_MODE_SIZE (mode).to_constant ()) - 2; + bool uindex = info.type == ADDRESS_REG_UREG; + + const char *const insn[][2] = { + { + "th.fs%srw\t%%z1,%%0", + "th.fs%srd\t%%z1,%%0" + }, + { + "th.fl%srw\t%%0,%%1", + "th.fl%srd\t%%0,%%1" + } + }; + + snprintf (buf, sizeof (buf), insn[load][index], uindex ? "u" : ""); + + return buf; +} + /* Return true if X is a valid address for T-Head's memory addressing modes for machine mode MODE. If it is, fill in INFO appropriately (if non-NULL). If STRICT_P is true then REG_OK_STRICT is in effect. */ @@ -804,25 +851,37 @@ th_output_move (rtx dest, rtx src) if (dest_code == REG && src_code == MEM) { rtx x = XEXP (src, 0); - if (GET_MODE_CLASS (mode) == MODE_INT) + if (GET_MODE_CLASS (mode) == MODE_INT + || (GET_MODE_CLASS (mode) == MODE_FLOAT && GP_REG_P (REGNO (dest)))) { if ((insn = th_memidx_output_index (x, mode, true))) return insn; if ((insn = th_memidx_output_modify (x, mode, true))) return insn; } + else if (GET_MODE_CLASS (mode) == MODE_FLOAT && HARDFP_REG_P (REGNO (dest))) + { + if ((insn = th_fmemidx_output_index (x, mode, true))) + return insn; + } } else if (dest_code == MEM && (src_code == REG || src == CONST0_RTX (mode))) { rtx x = XEXP (dest, 0); if (GET_MODE_CLASS (mode) == MODE_INT - || src == CONST0_RTX (mode)) + || src == CONST0_RTX (mode) + || (GET_MODE_CLASS (mode) == MODE_FLOAT && GP_REG_P (REGNO (src)))) { if ((insn = th_memidx_output_index (x, mode, false))) return insn; if ((insn = th_memidx_output_modify (x, mode, false))) return insn; } + else if (GET_MODE_CLASS (mode) == MODE_FLOAT && HARDFP_REG_P (REGNO (src))) + { + if ((insn = th_fmemidx_output_index (x, mode, false))) + return insn; + } } return NULL; } diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index e9a8bf579d0..1840245748d 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -587,15 +587,24 @@ (define_insn "*th_memidx_bb_extendqi2" [(set_attr "move_type" "shift_shift,load,load,load,load,load") (set_attr "mode" "")]) +;; All modes that are supported by XTheadMemIdx (define_mode_iterator TH_M_ANYI [(QI "TARGET_XTHEADMEMIDX") (HI "TARGET_XTHEADMEMIDX") (SI "TARGET_XTHEADMEMIDX") (DI "TARGET_64BIT && TARGET_XTHEADMEMIDX")]) +;; All modes that are supported by XTheadFMemIdx +(define_mode_iterator TH_M_ANYF [(SF "TARGET_HARD_FLOAT && TARGET_XTHEADFMEMIDX") + (DF "TARGET_DOUBLE_FLOAT && TARGET_XTHEADFMEMIDX")]) + ;; All non-extension modes that are supported by XTheadMemIdx (define_mode_iterator TH_M_NOEXTI [(SI "!TARGET_64BIT && TARGET_XTHEADMEMIDX") (DI "TARGET_64BIT && TARGET_XTHEADMEMIDX")]) +;; All non-extension modes that are supported by XTheadFMemIdx +(define_mode_iterator TH_M_NOEXTF [(SF "TARGET_HARD_FLOAT && TARGET_XTHEADFMEMIDX") + (DF "TARGET_DOUBLE_FLOAT && TARGET_XTHEADFMEMIDX")]) + ;; XTheadMemIdx optimizations ;; All optimizations attempt to improve the operand utilization of ;; XTheadMemIdx instructions, where one sign or zero extended @@ -812,4 +821,156 @@ (define_insn_and_split "*th_memidx_UZ_c" (match_dup 0))] ) +;; XTheadFMemIdx + +(define_insn "*th_fmemidx_movsf_hardfloat" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,th_m_mir,f,th_m_miu") + (match_operand:SF 1 "move_operand" " th_m_mir,f,th_m_miu,f"))] + "TARGET_HARD_FLOAT && TARGET_XTHEADFMEMIDX + && (register_operand (operands[0], SFmode) + || reg_or_0_operand (operands[1], SFmode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fpload,fpstore,fpload,fpstore") + (set_attr "mode" "SF")]) + +(define_insn "*th_fmemidx_movdf_hardfloat_rv64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,th_m_mir,f,th_m_miu") + (match_operand:DF 1 "move_operand" " th_m_mir,f,th_m_miu,f"))] + "TARGET_64BIT && TARGET_DOUBLE_FLOAT && TARGET_XTHEADFMEMIDX + && (register_operand (operands[0], DFmode) + || reg_or_0_operand (operands[1], DFmode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fpload,fpstore,fpload,fpstore") + (set_attr "mode" "DF")]) + +;; XTheadFMemIdx optimizations +;; Similar like XTheadMemIdx optimizations, but less cases. +;; Note, that we might get GP registers in FP-mode (reg:DF a2) +;; which cannot be handled by the XTheadFMemIdx instructions. +;; This might even happend after register allocation. +;; We could implement splitters that undo the combiner results +;; if "after_reload && !HARDFP_REG_P (operands[0])", but this +;; raises even more questions (e.g. split into what?). +;; So let's solve this by simply requiring XTheadMemIdx +;; which provides the necessary instructions to cover this case. + +(define_insn_and_split "*th_fmemidx_I_a" + [(set (match_operand:TH_M_NOEXTF 0 "register_operand" "=f") + (mem:TH_M_NOEXTF (plus:X + (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")) + (match_operand:X 3 "register_operand" "r"))))] + "TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX + && CONST_INT_P (operands[2]) + && pow2p_hwi (INTVAL (operands[2])) + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 1, 3)" + "#" + "&& 1" + [(set (match_dup 0) + (mem:TH_M_NOEXTF (plus:X + (match_dup 3) + (ashift:X (match_dup 1) (match_dup 2)))))] + { operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); + } +) + +(define_insn_and_split "*th_fmemidx_I_c" + [(set (mem:TH_M_ANYF (plus:X + (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")) + (match_operand:X 3 "register_operand" "r"))) + (match_operand:TH_M_ANYF 0 "register_operand" "f"))] + "TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX + && CONST_INT_P (operands[2]) + && pow2p_hwi (INTVAL (operands[2])) + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 1, 3)" + "#" + "&& 1" + [(set (mem:TH_M_ANYF (plus:X + (match_dup 3) + (ashift:X (match_dup 1) (match_dup 2)))) + (match_dup 0))] + { operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); + } +) + +(define_insn_and_split "*th_fmemidx_US_a" + [(set (match_operand:TH_M_NOEXTF 0 "register_operand" "=f") + (mem:TH_M_NOEXTF (plus:DI + (and:DI + (mult:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")) + (match_operand:DI 3 "immediate_operand" "i")) + (match_operand:DI 4 "register_operand" "r"))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX + && CONST_INT_P (operands[2]) + && pow2p_hwi (INTVAL (operands[2])) + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 1, 3) + && CONST_INT_P (operands[3]) + && (INTVAL (operands[3]) >> exact_log2 (INTVAL (operands[2]))) == 0xffffffff" + "#" + "&& 1" + [(set (match_dup 0) + (mem:TH_M_NOEXTF (plus:DI + (match_dup 4) + (ashift:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))))] + { operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); + } +) + +(define_insn_and_split "*th_fmemidx_US_c" + [(set (mem:TH_M_ANYF (plus:DI + (and:DI + (mult:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")) + (match_operand:DI 3 "immediate_operand" "i")) + (match_operand:DI 4 "register_operand" "r"))) + (match_operand:TH_M_ANYF 0 "register_operand" "f"))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX + && CONST_INT_P (operands[2]) + && pow2p_hwi (INTVAL (operands[2])) + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 1, 3) + && CONST_INT_P (operands[3]) + && (INTVAL (operands[3]) >> exact_log2 (INTVAL (operands[2]))) == 0xffffffff" + "#" + "&& 1" + [(set (mem:TH_M_ANYF (plus:DI + (match_dup 4) + (ashift:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))) + (match_dup 0))] + { operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); + } +) + +(define_insn_and_split "*th_fmemidx_UZ_a" + [(set (match_operand:TH_M_NOEXTF 0 "register_operand" "=f") + (mem:TH_M_NOEXTF (plus:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r"))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX + && (!HARD_REGISTER_NUM_P (REGNO (operands[0])) || HARDFP_REG_P (REGNO (operands[0])))" + "#" + "&& 1" + [(set (match_dup 0) + (mem:TH_M_NOEXTF (plus:DI + (match_dup 2) + (zero_extend:DI (match_dup 1)))))] +) + +(define_insn_and_split "*th_fmemidx_UZ_c" + [(set (mem:TH_M_ANYF (plus:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r"))) + (match_operand:TH_M_ANYF 0 "register_operand" "f"))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX" + "#" + "&& 1" + [(set (mem:TH_M_ANYF (plus:DI + (match_dup 2) + (zero_extend:DI (match_dup 1)))) + (match_dup 0))] +) + (include "thead-peephole.md") diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c new file mode 100644 index 00000000000..931770037ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +LR_REG_IMM_UPD(double, 2) +#endif + +SR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +SR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c new file mode 100644 index 00000000000..fe4be4d095c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +LR_REG_IMM_UPD(double, 2) +#endif + +SR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +SR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c new file mode 100644 index 00000000000..dff76894802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +LR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flrd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +SR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +SR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsrd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c new file mode 100644 index 00000000000..5d8800863b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +LR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flrd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +SR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +SR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsrd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c new file mode 100644 index 00000000000..63e96be3741 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +LRU_REG_IMM_UPD(double, 2) +#endif + +SRU_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +SRU_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c new file mode 100644 index 00000000000..8100720bbe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +LRU_REG_IMM_UPD(double, 2) +#endif + +SRU_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +SRU_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c new file mode 100644 index 00000000000..a37473469be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flurw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +LRU_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flurd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +SRU_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsurw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +SRU_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsurd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c new file mode 100644 index 00000000000..ca4783b400b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadmemidx_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flurw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +LRU_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flurd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +SRU_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsurw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +SRU_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsurd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ +