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kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH V3 11/11] RISC-V: P11: Adjust and add testcases Date: Thu, 19 Oct 2023 16:33:33 +0800 Message-Id: <20231019083333.2052340-12-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20231019083333.2052340-1-lehua.ding@rivai.ai> References: <20231019083333.2052340-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780172469753814342 X-GMAIL-MSGID: 1780172469753814342 PR target/111037 PR target/111234 PR target/111725 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-1.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Adjust. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Adjust. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Adjust. * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Adjust. * gcc.target/riscv/rvv/base/pr111037-1.c: Moved to... * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: ...here. * gcc.target/riscv/rvv/base/pr111037-2.c: Moved to... * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: ...here. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust. * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: New test. * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: New test. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: New test. --- .../gcc.target/riscv/rvv/base/scalar_move-1.c | 2 +- .../riscv/rvv/vsetvl/avl_single-104.c | 35 +++++++++++++++ .../riscv/rvv/vsetvl/avl_single-105.c | 23 ++++++++++ .../riscv/rvv/vsetvl/avl_single-106.c | 34 ++++++++++++++ .../riscv/rvv/vsetvl/avl_single-107.c | 41 +++++++++++++++++ .../riscv/rvv/vsetvl/avl_single-108.c | 41 +++++++++++++++++ .../riscv/rvv/vsetvl/avl_single-109.c | 45 +++++++++++++++++++ .../riscv/rvv/vsetvl/avl_single-23.c | 7 +-- .../riscv/rvv/vsetvl/avl_single-46.c | 3 +- .../riscv/rvv/vsetvl/avl_single-84.c | 5 +-- .../riscv/rvv/vsetvl/avl_single-89.c | 8 ++-- .../riscv/rvv/vsetvl/avl_single-95.c | 2 +- .../riscv/rvv/vsetvl/imm_bb_prop-1.c | 7 +-- .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c | 2 +- .../riscv/rvv/{base => vsetvl}/pr111037-1.c | 0 .../riscv/rvv/{base => vsetvl}/pr111037-2.c | 0 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 16 +++++++ .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c | 16 +++++++ .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 ++--- .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 ++--- .../riscv/rvv/vsetvl/vlmax_conflict-12.c | 1 - .../riscv/rvv/vsetvl/vlmax_conflict-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c | 4 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 4 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +- 26 files changed, 288 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-1.c (100%) rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-2.c (100%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-1.c index 18349132a88..c833d8989e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-1.c @@ -46,8 +46,8 @@ int32_t foo3 (int32_t *base, size_t vl) ** vl1re32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vsetvli\tzero,[a-x0-9]+,e32,m1,t[au],m[au] ** vadd.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ -** vsetvli\tzero,[a-x0-9]+,e32,m2,t[au],m[au] ** vmv.x.s\t[a-x0-9]+,\s*v[0-9]+ +** vsetvli\tzero,[a-x0-9]+,e32,m2,t[au],m[au] ** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ ** vmv.x.s\t[a-x0-9]+,\s*v[0-9]+ ** ret diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c new file mode 100644 index 00000000000..fb3577dcb98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int cond, int vl, int *in, int *out, int n) +{ + if (cond > 30) + { + vint32m1_t v = __riscv_vle32_v_i32m1 ((int32_t *) in, vl); + __riscv_vse32_v_i32m1 ((int32_t *) out, v, vl); + } + else if (cond < 10) + { + vint8mf4_t v = __riscv_vle8_v_i8mf4 ((int8_t *) in, vl); + v = __riscv_vle8_v_i8mf4_tu (v, (int8_t *) in + 10, vl); + __riscv_vse8_v_i8mf4 ((int8_t *) out, v, vl); + } + else + { + vl = vl * 2; + } + + for (int i = 0; i < n; i += 1) + { + vint16mf2_t v = __riscv_vle16_v_i16mf2 ((int16_t *) in + i, vl); + v = __riscv_vle16_v_i16mf2_tu (v, (int16_t *) in + i + 10, vl); + v = __riscv_vadd_vv_i16mf2 (v, v, vl); + __riscv_vse16_v_i16mf2 ((int16_t *) out + i, v, vl); + } +} + +/* { dg-final { scan-assembler-not {vsetvli\s+zero,zero,e16,mf2,t[au],m[au]} { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c new file mode 100644 index 00000000000..708a3bdf455 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int i, int n, int m, int32_t *in, int32_t *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, i); + __riscv_vse32_v_i32m1 (out, v, i); + for (; i < n; i += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, i); + __riscv_vse32_v_i32m1 (out + i, v, i); + for (int j = 0; j < m; j += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i * n + j, j); + __riscv_vse32_v_i32m1 (out + i * n + j, v, i); + } + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c new file mode 100644 index 00000000000..e63d52d8ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int vl, int n, int m, int32_t *in, int32_t *out) +{ + size_t avl; + if (m > 10) + { + avl = __riscv_vsetvl_e8mf4 (vl); + vint8mf4_t v = __riscv_vle8_v_i8mf4 ((int8_t *) in + 10, avl); + v = __riscv_vadd_vv_i8mf4 (v, v, avl); + __riscv_vse8_v_i8mf4 ((int8_t *) out + 10, v, avl); + } + else + { + avl = __riscv_vsetvl_e16mf2 (vl); + vint16mf2_t v = __riscv_vle16_v_i16mf2 ((int16_t *) in + 10, avl); + v = __riscv_vadd_vv_i16mf2 (v, v, avl); + __riscv_vse16_v_i16mf2 ((int16_t *) out + 10, v, avl); + } + + for (int i = 0; i < n; i += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, avl); + v = __riscv_vadd_vv_i32m1 (v, v, avl); + __riscv_vse32_v_i32m1 (out + i, v, avl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\tzero,zero,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c new file mode 100644 index 00000000000..e424b4ba435 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int vl, int n, int m, int32_t *in, int32_t *out) +{ + size_t avl; + if (m > 10) + { + avl = __riscv_vsetvl_e8mf4 (vl); + vint8mf4_t v = __riscv_vle8_v_i8mf4 ((int8_t *) in + 10, avl); + v = __riscv_vadd_vv_i8mf4 (v, v, avl); + __riscv_vse8_v_i8mf4 ((int8_t *) out + 10, v, avl); + } + else if (m > -10) + { + avl = __riscv_vsetvl_e16mf2 (vl); + vint16mf2_t v = __riscv_vle16_v_i16mf2 ((int16_t *) in + 10, avl); + v = __riscv_vadd_vv_i16mf2 (v, v, avl); + __riscv_vse16_v_i16mf2 ((int16_t *) out + 10, v, avl); + } + else + { + avl = __riscv_vsetvl_e64m2 (vl); + vint64m2_t v = __riscv_vle64_v_i64m2 ((int64_t *) in + 10, avl); + v = __riscv_vadd_vv_i64m2 (v, v, avl); + __riscv_vse64_v_i64m2 ((int64_t *) out + 10, v, avl); + } + + for (int i = 0; i < n; i += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, avl); + v = __riscv_vadd_vv_i32m1 (v, v, avl); + __riscv_vse32_v_i32m1 (out + i, v, avl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\tzero,zero,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c new file mode 100644 index 00000000000..95f1a955296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int vl, int n, int m, int32_t *in, int32_t *out) +{ + size_t avl; + if (m > 10) + { + avl = __riscv_vsetvl_e8mf4 (vl); + vint8mf4_t v = __riscv_vle8_v_i8mf4 ((int8_t *) in + 10, avl); + v = __riscv_vadd_vv_i8mf4 (v, v, avl); + __riscv_vse8_v_i8mf4 ((int8_t *) out + 10, v, avl); + } + else if (m > -10) + { + avl = __riscv_vsetvl_e16mf2 (vl); + vint16mf2_t v = __riscv_vle16_v_i16mf2 ((int16_t *) in + 10, avl); + v = __riscv_vadd_vv_i16mf2 (v, v, avl); + __riscv_vse16_v_i16mf2 ((int16_t *) out + 10, v, avl); + } + else + { + avl = __riscv_vsetvl_e64m4 (vl); + vint64m4_t v = __riscv_vle64_v_i64m4 ((int64_t *) in + 10, avl); + v = __riscv_vadd_vv_i64m4 (v, v, avl); + __riscv_vse64_v_i64m4 ((int64_t *) out + 10, v, avl); + } + + for (int i = 0; i < n; i += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, avl); + v = __riscv_vadd_vv_i32m1 (v, v, avl); + __riscv_vse32_v_i32m1 (out + i, v, avl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-not {vsetvli\tzero,zero,e32,m1,t[au],m[au]} { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c new file mode 100644 index 00000000000..a45e52befbf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ + +#include "riscv_vector.h" + +void +foo (int vl, int n, int m, int32_t *in, int32_t *out) +{ + size_t avl; + if (m > 10) + { + avl = __riscv_vsetvl_e8mf4 (vl); + vint8mf4_t v = __riscv_vle8_v_i8mf4 ((int8_t *) in + 10, avl); + v = __riscv_vadd_vv_i8mf4 (v, v, avl); + __riscv_vse8_v_i8mf4 ((int8_t *) out + 10, v, avl); + } + else if (m > -10) + { + avl = __riscv_vsetvl_e16mf2 (vl); + vint16mf2_t v = __riscv_vle16_v_i16mf2 ((int16_t *) in + 10, avl); + v = __riscv_vadd_vv_i16mf2 (v, v, avl); + __riscv_vse16_v_i16mf2 ((int16_t *) out + 10, v, avl); + } + else if (m > -100) + { + avl = __riscv_vsetvl_e64m4 (vl); + vint64m4_t v = __riscv_vle64_v_i64m4 ((int64_t *) in + 10, avl); + v = __riscv_vadd_vv_i64m4 (v, v, avl); + __riscv_vse64_v_i64m4 ((int64_t *) out + 10, v, avl); + } + else + { + avl = 123; + } + + for (int i = 0; i < n; i += 1) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, avl); + v = __riscv_vadd_vv_i32m1 (v, v, avl); + __riscv_vse32_v_i32m1 (out + i, v, avl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-not {vsetvli\tzero,zero,e32,m1,t[au],m[au]} { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c index 708f04b46be..ec59d58c258 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c @@ -7,7 +7,7 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) { vbool64_t mask = *(vbool64_t*) (in + 1000000); for (size_t j = 0; j < m; j++){ - + size_t vl = 101; for (size_t i = 0; i < n; i++) { @@ -20,7 +20,7 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) { vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl); __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl); - + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl); __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl); } @@ -29,6 +29,7 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O1" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { { any-opts "-Os" "-O2" } && { no-opts "-g" "-funroll-loops" } } } } } */ /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,101} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,102} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c index 99fdd67db64..a60674d9179 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c @@ -21,5 +21,6 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int cond, size_t vl) } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c index b3e90d260e7..a584dd97dc0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c @@ -17,7 +17,6 @@ double f0 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned c } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*3,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c index 9f850880ae5..65bff4d8ddc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c @@ -11,11 +11,11 @@ float f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned con { vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), __riscv_vsetvlmax_e32mf2 ()); __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, __riscv_vsetvlmax_e32mf2 ()); - + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), __riscv_vsetvlmax_e32mf2 ()); __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, __riscv_vsetvlmax_e32mf2 ()); } - + vfloat32m1_t v = *(vfloat32m1_t*)(in + 300000); for (size_t i = 0; i < n; i++) { @@ -25,7 +25,7 @@ float f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned con return __riscv_vfmv_f_s_f32m1_f32 (v); } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*3,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*3,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c index 5dac25ee59c..128a62953e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c @@ -15,6 +15,6 @@ float f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned con *(vfloat32m1_t*)(out + 100000) = v; } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*3,\s*e64,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*3,\s*e32,\s*m2,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-not {vsetvli} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c index ed32a40f5e7..691980f04e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c @@ -16,17 +16,18 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) for (int i = 0 ; i < n * n; i++) out[i] = out[i] + out[i]; - + for (int i = 0 ; i < n * n * n; i++) out[i] = out[i] * out[i]; for (int i = 0 ; i < n * n * n * n; i++) out[i] = out[i] * out[i]; - + for (int i = 0 ; i < n * n * n * n; i++) { vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, 5); __riscv_vse8_v_i8mf8 (out + 900 + i, v, 5); } } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c index 5f6647bb916..e87dc032b9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c @@ -23,5 +23,5 @@ void f (int32_t * a, int32_t * b, int n) } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*(?:e8,mf4|e32,m1),\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c index 8656e473117..7a9882b77e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c @@ -17,4 +17,4 @@ void f (int32_t *a, int32_t *b, int n) } } -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c similarity index 100% rename from gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c rename to gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c similarity index 100% rename from gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c rename to gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c new file mode 100644 index 00000000000..0f40642c8b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void foo(_Float16 y, int16_t z, int64_t *i64p) +{ + vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); + vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); + vint16m1_t vz =__riscv_vmv_s_x_i16m1 (z, 1); + vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); + asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy), "vr" (vz)); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c new file mode 100644 index 00000000000..1a0fcf72326 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void foo(_Float16 y, int16_t z, int64_t *i64p) +{ + vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); + vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); + vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); + vint16m1_t vz =__riscv_vmv_s_x_i16m1 (z, 1); + asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy), "vr" (vz)); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c index 2ec9487a6c6..d0fdc5fadb0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c @@ -88,8 +88,8 @@ void f (void * restrict in, void * restrict out, int n, int cond) } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 19 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c index bcafce36895..d0e75258188 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c @@ -80,8 +80,8 @@ void f (void * restrict in, void * restrict out, int n, int cond) } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 17 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c index d1611ddf345..00a75948ba5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c @@ -36,4 +36,3 @@ void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out, } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c index 3e89cfc107b..88a565fd891 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c @@ -27,4 +27,4 @@ void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out, } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c index 6157a2c7f12..1ea248dce88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c @@ -4,7 +4,7 @@ #include "riscv_vector.h" void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) { - + size_t vl; if (cond) vl = __riscv_vsetvl_e32m1(avl); @@ -18,5 +18,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c index 7ad277e0266..5799220ec77 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c @@ -16,5 +16,7 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n) { } } -/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c index fc4015e66b8..e3d069ff32a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c @@ -33,4 +33,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) { /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 6 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */