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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m2-20020a05620a24c200b007743658a2besi4924892qkn.499.2023.10.15.19.01.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Oct 2023 19:01:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E93F3858423 for ; Mon, 16 Oct 2023 02:01:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id BBC323858415 for ; Mon, 16 Oct 2023 02:01:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BBC323858415 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BBC323858415 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697421673; cv=none; b=A5AojZ0CxkPf25d7/FjADc8XUWF7p1TobuqGPGY3yeR/NPHg+5eDZbVGMKYFuPUnR3a7svYOXqhXNhrgulWc0KhzMjYQyjGQSrsCoNZ+0CXewdm4PdczDv64jHUUBKwjhuc7k4hpqiHSByzO7uxONUDysAXceedgc7QD+4EhJcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697421673; c=relaxed/simple; bh=R3hZGIDSbaH5pcawj+/5WIcu2WoMrjLqpvgJ4BORogo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=hkIaI6Nmhbu6KJU8qeCjQFuCCpwXTvs1Un8t7Bb4vVjLbpPSEOaIbKEwNpUZMrVLamqyBl3TF4ijbkA26XqwvXsd5NnupSZlCcgRLnIs65PI4KgSHu6LodaV951Z7T+lQLLnzRoN0u6epDLznW0L+PXROc1kJthVOI5DyjVFr7I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qsCuI-0005W7-E7 for gcc-patches@gcc.gnu.org; Sun, 15 Oct 2023 22:01:01 -0400 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8Cx5_E1mSxl4zkyAA--.31106S3; Mon, 16 Oct 2023 10:00:21 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxbNwvmSxlz_4lAA--.14027S5; Mon, 16 Oct 2023 10:00:20 +0800 (CST) From: Jiahao Xu To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Jiahao Xu Subject: [PATCH 1/3] LoongArch:Implement avg and sad standard names. Date: Mon, 16 Oct 2023 10:00:12 +0800 Message-Id: <20231016020014.41979-2-xujiahao@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231016020014.41979-1-xujiahao@loongson.cn> References: <20231016020014.41979-1-xujiahao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxbNwvmSxlz_4lAA--.14027S5 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoWfJw13Cr15WrWxWr4rXFyUCFX_yoWkGw1xp3 97Gw18tr48JFs7Kw1vgFy5Jr47GFsrGF47ZasxGrZFkry7tr92q340yFZIqFyYyw4Yvr17 Xan3Ca12qryxKwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAF wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU2nYFDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=xujiahao@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779875665194864813 X-GMAIL-MSGID: 1779875665194864813 gcc/ChangeLog: * config/loongarch/lasx.md (avg3_floor, uavg3_floor, avg3_ceil, uavg3_ceil, ssadv16qi, usadv16qi): New patterns. * config/loongarch/lsx.md (avg3_floor, uavg3_floor, avg3_ceil, uavg3_ceil, ssadv16qi, usadv16qi): New patterns. gcc/testsuite/ChangeLog: * gcc.target/loongarch/avg-ceil-lasx.c: New test. * gcc.target/loongarch/avg-ceil-lsx.c: New test. * gcc.target/loongarch/avg-floor-lasx.c: New test. * gcc.target/loongarch/avg-floor-lsx.c: New test. * gcc.target/loongarch/sad-lasx.c.c: New test. * gcc.target/loongarch/sad-lsx.c: New test. diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 2bc5d47ed4a..483d78bb210 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -5171,3 +5171,77 @@ const0_rtx)); DONE; }) + +(define_expand "avg3_ceil" + [(match_operand:ILASX_WHB 0 "register_operand") + (match_operand:ILASX_WHB 1 "register_operand") + (match_operand:ILASX_WHB 2 "register_operand")] + "ISA_HAS_LASX" +{ + emit_insn (gen_lasx_xvavgr_s_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "uavg3_ceil" + [(match_operand:ILASX_WHB 0 "register_operand") + (match_operand:ILASX_WHB 1 "register_operand") + (match_operand:ILASX_WHB 2 "register_operand")] + "ISA_HAS_LASX" +{ + emit_insn (gen_lasx_xvavgr_u_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "avg3_floor" + [(match_operand:ILASX_WHB 0 "register_operand") + (match_operand:ILASX_WHB 1 "register_operand") + (match_operand:ILASX_WHB 2 "register_operand")] + "ISA_HAS_LASX" +{ + emit_insn (gen_lasx_xvavg_s_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "uavg3_floor" + [(match_operand:ILASX_WHB 0 "register_operand") + (match_operand:ILASX_WHB 1 "register_operand") + (match_operand:ILASX_WHB 2 "register_operand")] + "ISA_HAS_LASX" +{ + emit_insn (gen_lasx_xvavg_u_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "usadv32qi" + [(match_operand:V8SI 0 "register_operand") + (match_operand:V32QI 1 "register_operand") + (match_operand:V32QI 2 "register_operand") + (match_operand:V8SI 3 "register_operand")] + "ISA_HAS_LASX" +{ + rtx t1 = gen_reg_rtx (V32QImode); + rtx t2 = gen_reg_rtx (V16HImode); + rtx t3 = gen_reg_rtx (V8SImode); + emit_insn (gen_lasx_xvabsd_u_bu (t1, operands[1], operands[2])); + emit_insn (gen_lasx_xvhaddw_h_b (t2, t1, t1)); + emit_insn (gen_lasx_xvhaddw_w_h (t3, t2, t2)); + emit_insn (gen_addv8si3 (operands[0], t3, operands[3])); + DONE; +}) + +(define_expand "ssadv32qi" + [(match_operand:V8SI 0 "register_operand") + (match_operand:V32QI 1 "register_operand") + (match_operand:V32QI 2 "register_operand") + (match_operand:V8SI 3 "register_operand")] + "ISA_HAS_LASX" +{ + rtx t1 = gen_reg_rtx (V32QImode); + rtx t2 = gen_reg_rtx (V16HImode); + rtx t3 = gen_reg_rtx (V8SImode); + emit_insn (gen_lasx_xvabsd_s_b (t1, operands[1], operands[2])); + emit_insn (gen_lasx_xvhaddw_h_b (t2, t1, t1)); + emit_insn (gen_lasx_xvhaddw_w_h (t3, t2, t2)); + emit_insn (gen_addv8si3 (operands[0], t3, operands[3])); + DONE; +}) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 075f6ba569d..b63c6ff4dee 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -3581,6 +3581,80 @@ DONE; }) +(define_expand "avg3_ceil" + [(match_operand:ILSX_WHB 0 "register_operand") + (match_operand:ILSX_WHB 1 "register_operand") + (match_operand:ILSX_WHB 2 "register_operand")] + "ISA_HAS_LSX" +{ + emit_insn (gen_lsx_vavgr_s_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "uavg3_ceil" + [(match_operand:ILSX_WHB 0 "register_operand") + (match_operand:ILSX_WHB 1 "register_operand") + (match_operand:ILSX_WHB 2 "register_operand")] + "ISA_HAS_LSX" +{ + emit_insn (gen_lsx_vavgr_u_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "avg3_floor" + [(match_operand:ILSX_WHB 0 "register_operand") + (match_operand:ILSX_WHB 1 "register_operand") + (match_operand:ILSX_WHB 2 "register_operand")] + "ISA_HAS_LSX" +{ + emit_insn (gen_lsx_vavg_s_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "uavg3_floor" + [(match_operand:ILSX_WHB 0 "register_operand") + (match_operand:ILSX_WHB 1 "register_operand") + (match_operand:ILSX_WHB 2 "register_operand")] + "ISA_HAS_LSX" +{ + emit_insn (gen_lsx_vavg_u_ (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "usadv16qi" + [(match_operand:V4SI 0 "register_operand") + (match_operand:V16QI 1 "register_operand") + (match_operand:V16QI 2 "register_operand") + (match_operand:V4SI 3 "register_operand")] + "ISA_HAS_LSX" +{ + rtx t1 = gen_reg_rtx (V16QImode); + rtx t2 = gen_reg_rtx (V8HImode); + rtx t3 = gen_reg_rtx (V4SImode); + emit_insn (gen_lsx_vabsd_u_bu (t1, operands[1], operands[2])); + emit_insn (gen_lsx_vhaddw_h_b (t2, t1, t1)); + emit_insn (gen_lsx_vhaddw_w_h (t3, t2, t2)); + emit_insn (gen_addv4si3 (operands[0], t3, operands[3])); + DONE; +}) + +(define_expand "ssadv16qi" + [(match_operand:V4SI 0 "register_operand") + (match_operand:V16QI 1 "register_operand") + (match_operand:V16QI 2 "register_operand") + (match_operand:V4SI 3 "register_operand")] + "ISA_HAS_LSX" +{ + rtx t1 = gen_reg_rtx (V16QImode); + rtx t2 = gen_reg_rtx (V8HImode); + rtx t3 = gen_reg_rtx (V4SImode); + emit_insn (gen_lsx_vabsd_s_b (t1, operands[1], operands[2])); + emit_insn (gen_lsx_vhaddw_h_b (t2, t1, t1)); + emit_insn (gen_lsx_vhaddw_w_h (t3, t2, t2)); + emit_insn (gen_addv4si3 (operands[0], t3, operands[3])); + DONE; +}) + (define_insn "lsx_vwev_d_w" [(set (match_operand:V2DI 0 "register_operand" "=f") (addsubmul:V2DI diff --git a/gcc/testsuite/gcc.target/loongarch/avg-ceil-lasx.c b/gcc/testsuite/gcc.target/loongarch/avg-ceil-lasx.c new file mode 100644 index 00000000000..a4fc7a63f97 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/avg-ceil-lasx.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlasx" } */ +/* { dg-final { scan-assembler "xvavgr.b" } } */ +/* { dg-final { scan-assembler "xvavgr.bu" } } */ +/* { dg-final { scan-assembler "xvavgr.hu" } } */ +/* { dg-final { scan-assembler "xvavgr.h" } } */ + +#define N 1024 + +#define TEST(TYPE, NAME) \ + TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \ + void f_##NAME (void) \ + { \ + int i; \ + for (i = 0; i < N; i++) \ + a_##NAME[i] = (b_##NAME[i] + c_##NAME[i] + 1) >> 1; \ + } + +TEST(char, 1); +TEST(short, 2); +TEST(unsigned char, 3); +TEST(unsigned short, 4); diff --git a/gcc/testsuite/gcc.target/loongarch/avg-ceil-lsx.c b/gcc/testsuite/gcc.target/loongarch/avg-ceil-lsx.c new file mode 100644 index 00000000000..7aae01600d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/avg-ceil-lsx.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlsx" } */ +/* { dg-final { scan-assembler "vavgr.b" } } */ +/* { dg-final { scan-assembler "vavgr.bu" } } */ +/* { dg-final { scan-assembler "vavgr.hu" } } */ +/* { dg-final { scan-assembler "vavgr.h" } } */ + +#define N 1024 + +#define TEST(TYPE, NAME) \ + TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \ + void f_##NAME (void) \ + { \ + int i; \ + for (i = 0; i < N; i++) \ + a_##NAME[i] = (b_##NAME[i] + c_##NAME[i] + 1) >> 1; \ + } + +TEST(char, 1); +TEST(short, 2); +TEST(unsigned char, 3); +TEST(unsigned short, 4); diff --git a/gcc/testsuite/gcc.target/loongarch/avg-floor-lasx.c b/gcc/testsuite/gcc.target/loongarch/avg-floor-lasx.c new file mode 100644 index 00000000000..da6956f6f91 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/avg-floor-lasx.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlasx" } */ +/* { dg-final { scan-assembler "xvavg.b" } } */ +/* { dg-final { scan-assembler "xvavg.bu" } } */ +/* { dg-final { scan-assembler "xvavg.hu" } } */ +/* { dg-final { scan-assembler "xvavg.h" } } */ + +#define N 1024 + +#define TEST(TYPE, NAME) \ + TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \ + void f_##NAME (void) \ + { \ + int i; \ + for (i = 0; i < N; i++) \ + a_##NAME[i] = (b_##NAME[i] + c_##NAME[i]) >> 1; \ + } + +TEST(char, 1); +TEST(short, 2); +TEST(unsigned char, 3); +TEST(unsigned short, 4); diff --git a/gcc/testsuite/gcc.target/loongarch/avg-floor-lsx.c b/gcc/testsuite/gcc.target/loongarch/avg-floor-lsx.c new file mode 100644 index 00000000000..d16c23ac0cc --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/avg-floor-lsx.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlsx" } */ +/* { dg-final { scan-assembler "vavg.b" } } */ +/* { dg-final { scan-assembler "vavg.bu" } } */ +/* { dg-final { scan-assembler "vavg.hu" } } */ +/* { dg-final { scan-assembler "vavg.h" } } */ + +#define N 1024 + +#define TEST(TYPE, NAME) \ + TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \ + void f_##NAME (void) \ + { \ + int i; \ + for (i = 0; i < N; i++) \ + a_##NAME[i] = (b_##NAME[i] + c_##NAME[i]) >> 1; \ + } + +TEST(char, 1); +TEST(short, 2); +TEST(unsigned char, 3); +TEST(unsigned short, 4); diff --git a/gcc/testsuite/gcc.target/loongarch/sad-lasx.c b/gcc/testsuite/gcc.target/loongarch/sad-lasx.c new file mode 100644 index 00000000000..47ca4039489 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sad-lasx.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlasx" } */ + +#define N 1024 + +#define TEST(SIGN) \ + SIGN char a_##SIGN[N], b_##SIGN[N]; \ + int f_##SIGN (void) \ + { \ + int i, sum = 0; \ + for (i = 0; i < N; i++) \ + sum += __builtin_abs (a_##SIGN[i] - b_##SIGN[i]);; \ + return sum; \ + } + +TEST(signed); +TEST(unsigned); + +/* { dg-final { scan-assembler {\txvabsd.bu\t} } } */ +/* { dg-final { scan-assembler {\txvabsd.b\t} } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/sad-lsx.c b/gcc/testsuite/gcc.target/loongarch/sad-lsx.c new file mode 100644 index 00000000000..2aadf3d9309 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sad-lsx.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlsx" } */ + +#define N 1024 + +#define TEST(SIGN) \ + SIGN char a_##SIGN[N], b_##SIGN[N]; \ + int f_##SIGN (void) \ + { \ + int i, sum = 0; \ + for (i = 0; i < N; i++) \ + sum += __builtin_abs (a_##SIGN[i] - b_##SIGN[i]);; \ + return sum; \ + } + +TEST(signed); +TEST(unsigned); + +/* { dg-final { scan-assembler {\tvabsd.bu\t} } } */ +/* { dg-final { scan-assembler {\tvabsd.b\t} } } */