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[8.43.85.97]) by mx.google.com with ESMTPS id q26-20020a05620a0c9a00b0077424168fa1si661522qki.629.2023.10.12.22.45.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 22:45:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 79A193857707 for ; Fri, 13 Oct 2023 05:45:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id CF4B03858404 for ; Fri, 13 Oct 2023 05:45:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CF4B03858404 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1697175922t56cqsif Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 13 Oct 2023 13:45:21 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 3M0okmaRx3gxWl28Tjlo6emB4xgF0F+iuA8vYabhVnZNm1B0pgxq2nXC8PQFq YAfop1DONO420LPFBJ9O1G/IkZpLDrJ2CTse9LSI0HnRE0puGgN8MDq9jyzyqPp40PPRUs1 VT5tu/ElBl9c47FjkyCcYB0/oA1NHgq7sqXwCEosz/lnH5hfTSNlhVkTc5la7Om3byER4Ph +4U++XxVHcgNgzI/wrCVQ2QYLlJxiZvCuApjvznIm4ZZWSqCGUVW49nnkiOfNihykU8W/oU 0F+l62Jnioz42SQ+UmJeteEuWnIylEEvtumYx6hAXzxIqsqY+hlF07DbfbzWgihorvx1WNL tyD7G/b5b9VrIiSupkY2T18FfUsEBc/y1fAjVlJuDNTgg4SKMoxAVgR5Y8mPwxw0NRYF0vz X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6788203710210677335 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, rguenther@suse.de, Juzhe-Zhong Subject: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Date: Fri, 13 Oct 2023 13:45:19 +0800 Message-Id: <20231013054519.461486-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779617973752324153 X-GMAIL-MSGID: 1779617973752324153 Like ARM SVE and GCN, add RVV. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-pr69907.c: Add RVV. --- gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index b348526b62f..f63b42a271a 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2) /* Disable for SVE because for long or variable-length vectors we don't get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, because there we can vectorize the epilogue using mixed vector sizes. - Likewise for AMD GCN. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */ + Likewise for AMD GCN and RVV. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */