diff mbox series

RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV

Message ID 20231013054519.461486-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Oct. 13, 2023, 5:45 a.m. UTC 
  Like ARM SVE and GCN, add RVV.

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.

---
 gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng Oct. 13, 2023, 6:01 a.m. UTC | #1 
LGTM

Juzhe-Zhong <juzhe.zhong@rivai.ai> 於 2023年10月12日 週四 22:45 寫道：

> Like ARM SVE and GCN, add RVV.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
>
> ---
>  gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> index b348526b62f..f63b42a271a 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
>  /* Disable for SVE because for long or variable-length vectors we don't
>     get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
>     because there we can vectorize the epilogue using mixed vector sizes.
> -   Likewise for AMD GCN.  */
> -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { !
> amdgcn*-*-* } } } } } */
> +   Likewise for AMD GCN and RVV.  */
> +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { !
> amdgcn*-*-* } && { ! riscv_v } } } } } } */
> --
> 2.36.3
>
>
juzhe.zhong@rivai.ai Oct. 13, 2023, 6:04 a.m. UTC | #2 
Thanks. Committed.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-10-13 14:01
To: Juzhe-Zhong
CC: GCC Patches; Jeff Law; Richard Biener
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
LGTM 

Juzhe-Zhong <juzhe.zhong@rivai.ai> 於 2023年10月12日 週四 22:45 寫道：
Like ARM SVE and GCN, add RVV.

gcc/testsuite/ChangeLog:

        * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.

---
 gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
 /* Disable for SVE because for long or variable-length vectors we don't
    get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
    because there we can vectorize the epilogue using mixed vector sizes.
-   Likewise for AMD GCN.  */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
+   Likewise for AMD GCN and RVV.  */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
-- 
2.36.3
Richard Biener Oct. 13, 2023, 11:59 a.m. UTC | #3 
On Fri, 13 Oct 2023, Juzhe-Zhong wrote:

> Like ARM SVE and GCN, add RVV.

Adding RVV when SVE or GCN is already there looks obvious to me, these
kind of changes are pre-approved.  No need for all the noise.

Thanks,
Richard.

> gcc/testsuite/ChangeLog:
> 
> 	* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
> 
> ---
>  gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> index b348526b62f..f63b42a271a 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
>  /* Disable for SVE because for long or variable-length vectors we don't
>     get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
>     because there we can vectorize the epilogue using mixed vector sizes.
> -   Likewise for AMD GCN.  */
> -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
> +   Likewise for AMD GCN and RVV.  */
> +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@  void foo(unsigned *p1, unsigned short *p2)
 /* Disable for SVE because for long or variable-length vectors we don't
    get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
    because there we can vectorize the epilogue using mixed vector sizes.
-   Likewise for AMD GCN.  */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
+   Likewise for AMD GCN and RVV.  */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */