diff mbox series

[v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

Message ID 20231012130644.561301-1-christoph.muellner@vrull.eu
State Unresolved
Headers
Series [v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Christoph Müllner Oct. 12, 2023, 1:06 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")

A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the tests to simply count instruction,
like it is done for similar tests.

Reported-by: Patrick O'Neill <patrick@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
	instruction reordering.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 .../gcc.target/riscv/xtheadcondmov-indirect.c | 89 ++++++-------------
 1 file changed, 29 insertions(+), 60 deletions(-)

Comments

Jeff Law Oct. 12, 2023, 4:12 p.m. UTC | #1 
On 10/12/23 07:06, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> 
> A recent change broke the xtheadcondmov-indirect tests, because the order of
> emitted instructions changed. Since the test is too strict when testing for
> a fixed instruction order, let's change the tests to simply count instruction,
> like it is done for similar tests.
> 
> Reported-by: Patrick O'Neill <patrick@rivosinc.com>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> 	instruction reordering.
OK for the trunk.

jeff
Kito Cheng Oct. 12, 2023, 6:28 p.m. UTC | #2 
Sorry for the late comment after Jeff say ok, but I guess we may
consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
disturbing from schedule like some of our test case in
gcc/testsuite/gcc.target/riscv/rvv?

On Thu, Oct 12, 2023 at 9:12 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 10/12/23 07:06, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> >
> > A recent change broke the xtheadcondmov-indirect tests, because the order of
> > emitted instructions changed. Since the test is too strict when testing for
> > a fixed instruction order, let's change the tests to simply count instruction,
> > like it is done for similar tests.
> >
> > Reported-by: Patrick O'Neill <patrick@rivosinc.com>
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> >       instruction reordering.
> OK for the trunk.
>
> jeff
Kito Cheng Oct. 12, 2023, 6:29 p.m. UTC | #3 
but anyway, I don't have a strong opinion for either way, just go
ahead no matter which one you choose.

On Thu, Oct 12, 2023 at 11:28 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Sorry for the late comment after Jeff say ok, but I guess we may
> consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
> disturbing from schedule like some of our test case in
> gcc/testsuite/gcc.target/riscv/rvv?
>
> On Thu, Oct 12, 2023 at 9:12 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
> >
> >
> >
> > On 10/12/23 07:06, Christoph Muellner wrote:
> > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > >
> > > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> > >
> > > A recent change broke the xtheadcondmov-indirect tests, because the order of
> > > emitted instructions changed. Since the test is too strict when testing for
> > > a fixed instruction order, let's change the tests to simply count instruction,
> > > like it is done for similar tests.
> > >
> > > Reported-by: Patrick O'Neill <patrick@rivosinc.com>
> > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > >       * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> > >       instruction reordering.
> > OK for the trunk.
> >
> > jeff
Jeff Law Oct. 13, 2023, 4:23 p.m. UTC | #4 
On 10/12/23 12:28, Kito Cheng wrote:
> Sorry for the late comment after Jeff say ok, but I guess we may
> consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
> disturbing from schedule like some of our test case in
> gcc/testsuite/gcc.target/riscv/rvv?
It wouldn't be a bad idea to bring more stability, particularly to tests 
which are expecting instructions in a specific order.  THat feels like 
it's likely a distinct change though.

jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
index c3253ba5239..427c9c1a41e 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
@@ -1,16 +1,11 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_xtheadcondmov -fno-sched-pressure" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadcondmov -fno-sched-pressure" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
 /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
 
-/*
-** ConEmv_imm_imm_reg:
-**	addi	a[0-9]+,a[0-9]+,-1000
-**	li	a[0-9]+,10
-**	th\.mvnez	a[0-9]+,a[0-9]+,a[0-9]+
-**	ret
-*/
+/* addi aX, aX, -1000
+   li aX, 10
+   th.mvnez aX, aX, aX  */
 int ConEmv_imm_imm_reg(int x, int y)
 {
   if (x == 1000)
@@ -18,13 +13,8 @@  int ConEmv_imm_imm_reg(int x, int y)
   return y;
 }
 
-/*
-** ConEmv_imm_reg_reg:
-**	addi	a[0-9]+,a[0-9]+,-1000
-**	th.mveqz	a[0-9]+,a[0-9]+,a[0-9]+
-**	mv	a[0-9]+,a[0-9]+
-**	ret
-*/
+/* addi	aX, aX, -1000
+   th.mveqz aX, aX, aX  */
 int ConEmv_imm_reg_reg(int x, int y, int z)
 {
   if (x == 1000)
@@ -32,13 +22,9 @@  int ConEmv_imm_reg_reg(int x, int y, int z)
   return z;
 }
 
-/*
-** ConEmv_reg_imm_reg:
-**	sub	a[0-9]+,a[0-9]+,a[0-9]+
-**	li	a[0-9]+,10
-**	th.mvnez	a[0-9]+,a[0-9]+,a[0-9]+
-**	ret
-*/
+/* sub aX, aX, aX
+   li aX, 10
+   th.mvnez aX, aX, aX  */
 int ConEmv_reg_imm_reg(int x, int y, int z)
 {
   if (x == y)
@@ -46,13 +32,8 @@  int ConEmv_reg_imm_reg(int x, int y, int z)
   return z;
 }
 
-/*
-** ConEmv_reg_reg_reg:
-**	sub	a[0-9]+,a[0-9]+,a[0-9]+
-**	th.mveqz	a[0-9]+,a[0-9]+,a[0-9]+
-**	mv	a[0-9]+,a[0-9]+
-**	ret
-*/
+/* sub aX, aX, aX
+   th.mveqz aX, aX, aX  */
 int ConEmv_reg_reg_reg(int x, int y, int z, int n)
 {
   if (x == y)
@@ -60,14 +41,10 @@  int ConEmv_reg_reg_reg(int x, int y, int z, int n)
   return n;
 }
 
-/*
-** ConNmv_imm_imm_reg:
-**	addi	a[0-9]+,a[0-9]+,-1000+
-**	li	a[0-9]+,9998336+
-**	addi	a[0-9]+,a[0-9]+,1664+
-**	th.mveqz	a[0-9]+,a[0-9]+,a[0-9]+
-**	ret
-*/
+/* addi aX, aX, -1000
+   li aX, 9998336
+   addi aX, aX, 1664
+   th.mveqz aX, aX, aX  */
 int ConNmv_imm_imm_reg(int x, int y)
 {
   if (x != 1000)
@@ -75,13 +52,8 @@  int ConNmv_imm_imm_reg(int x, int y)
   return y;
 }
 
-/*
-**ConNmv_imm_reg_reg:
-**	addi	a[0-9]+,a[0-9]+,-1000+
-**	th.mvnez	a[0-9]+,a[0-9]+,a[0-9]+
-**	mv	a[0-9]+,a[0-9]+
-**	ret
-*/
+/* addi aX, aX, 1000
+   th.mvnez aX, aX, aX  */
 int ConNmv_imm_reg_reg(int x, int y, int z)
 {
   if (x != 1000)
@@ -89,13 +61,9 @@  int ConNmv_imm_reg_reg(int x, int y, int z)
   return z;
 }
 
-/*
-**ConNmv_reg_imm_reg:
-**	sub	a[0-9]+,a[0-9]+,a[0-9]+
-**	li	a[0-9]+,10+
-**	th.mveqz	a[0-9]+,a[0-9]+,a[0-9]+
-**	ret
-*/
+/* sub aX, aX, aX
+   li aX, 10
+   th.mveqz aX, aX, aX  */
 int ConNmv_reg_imm_reg(int x, int y, int z)
 {
   if (x != y)
@@ -103,16 +71,17 @@  int ConNmv_reg_imm_reg(int x, int y, int z)
   return z;
 }
 
-/*
-**ConNmv_reg_reg_reg:
-**	sub	a[0-9]+,a[0-9]+,a[0-9]+
-**	th.mvnez	a[0-9]+,a[0-9]+,a[0-9]+
-**	mv	a[0-9]+,a[0-9]+
-**	ret
-*/
+/* sub aX, aX, aX
+   th.mvnez aX, aX, aX  */
 int ConNmv_reg_reg_reg(int x, int y, int z, int n)
 {
   if (x != y)
     return z;
   return n;
 }
+
+/* { dg-final { scan-assembler-times "addi\t" 5 } } */
+/* { dg-final { scan-assembler-times "li\t" 4 } } */
+/* { dg-final { scan-assembler-times "sub\t" 4 } } */
+/* { dg-final { scan-assembler-times "th.mveqz\t" 4 } } */
+/* { dg-final { scan-assembler-times "th.mvnez\t" 4 } } */