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[Committed] RISC-V: Add testcase for SCCVN optimization[PR111751]

Message ID 20231010114901.4178775-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series [Committed] RISC-V: Add testcase for SCCVN optimization[PR111751] |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Oct. 10, 2023, 11:49 a.m. UTC 
  Add testcase for PR111751 which has been fixed:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632474.html

	PR target/111751

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr111751.c: New test.

---
 .../gcc.target/riscv/rvv/autovec/pr111751.c   | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111751.c
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Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111751.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111751.c
new file mode 100644
index 00000000000..0f1e8a7d567
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111751.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#define N 16
+
+int foo1 ()
+{
+  int i;
+  char ia[N];
+  char ic[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+  char ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+
+  /* Not vectorizable, multiplication */
+  for (i = 0; i < N; i++)
+    {
+      ia[i] = ib[i] * ic[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (ia[i] != (char) (ib[i] * ic[i]))
+        __builtin_abort ();
+    }
+
+  return 0;
+}
+
+typedef int half_word;
+
+int foo2 ()
+{
+  int i;
+  half_word ia[N];
+  half_word ic[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+  half_word ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+
+  /* Not worthwhile, only 2 parts per int */
+  for (i = 0; i < N; i++)
+    {
+      ia[i] = ib[i] + ic[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (ia[i] != ib[i] + ic[i])
+        __builtin_abort ();
+    }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,0\s+ret} 2 } } */
+/* { dg-final { scan-assembler-not {vset} } } */