[x86] Refine predicate of operands[2] in divv4hf3 with register_operand.
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Commit Message
In the expander, it will emit below insn.
rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
but *vec_concat<mode> only allow register_operand.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
PR target/111745
* config/i386/mmx.md (divv4hf3): Refine predicate of
operands[2] with register_operand.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr111745.c: New test.
---
gcc/config/i386/mmx.md | 2 +-
gcc/testsuite/gcc.target/i386/pr111745.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr111745.c
@@ -1950,7 +1950,7 @@ (define_expand "divv4hf3"
[(set (match_operand:V4HF 0 "register_operand")
(div:V4HF
(match_operand:V4HF 1 "nonimmediate_operand")
- (match_operand:V4HF 2 "nonimmediate_operand")))]
+ (match_operand:V4HF 2 "register_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{
rtx op2 = gen_reg_rtx (V8HFmode);
new file mode 100644
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -ffloat-store -O2" } */
+
+char c;
+_Float16 __attribute__((__vector_size__ (4 * sizeof (_Float16)))) f;
+_Float16 __attribute__((__vector_size__ (2 * sizeof (_Float16)))) f1;
+
+void
+foo (void)
+{
+ f /= c;
+}
+
+void
+foo1 (void)
+{
+ f1 /= c;
+}