From patchwork Sun Oct 8 02:27:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 149676 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:403:3b70:6f57 with SMTP id x8csp1185869vqo; Sat, 7 Oct 2023 19:29:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4xaoVOsBAxSiVa+JvlmbidoNHL2ii70XAz0s/8rPRstN8A/M7xQJe5eKIYLKCeCaUlTxa X-Received: by 2002:a17:906:3cb2:b0:9ba:65e:7529 with SMTP id b18-20020a1709063cb200b009ba065e7529mr3217547ejh.68.1696732147235; Sat, 07 Oct 2023 19:29:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696732147; cv=none; d=google.com; s=arc-20160816; b=FCxcKWmZYY8pheEZJL64zpibZoxucscRuGGu5Ic2k9XSDXMqMdxMNZkNP0Y3w/bEKB dJ6V/IEoHnYzXAaOsZdtid9o8/FbXhN9AQ1k5fYjPZ/a4AsZSMpjB25iLqRN8cesqm0h Sa+JjhhsJRInrlDMCl962BKijim2WF+Isoq7AgfZKRF34aIQ/4UhK8ic5F/qjUhwYMJK H2wpsPM+VgH6Ae0DRwiekMh91OfVeS+LLxLjdlMNpjaX4HvIjktaM7mxjl9Te/HQoQf2 QvGinhshUsg+D5mVKmxNQRhJO2ms0TP8hqH1Dmapa+BZiUtOEsHSTmL6Gv9YkCs4PizO URtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=Db89yRs5PmpaTXcrWd2ae2RK9dCpLrYyOV6T80TmNss=; fh=ChXOctppJn0KECDRINafwUY5xHRufGHaa0Ju9pddrcQ=; b=nhIUpu3TZfiDr6wrNK2UORlEC6qqnrX5sww8LkK1qV7rsN11h5cM1oqvYBYr8JSWIf 3A15ecXoD5LBOHjq1R5kjDu5rL/wJuUF6AIv2l/7NyDgn04uMCwzN72lsFxXnO4baCY3 oA4GG101Pl07n+/RckhBnmmH/QkSbO9ECsYOZVJtHTS/J+iK3bWNwPXpi30VHT7eo1jF ZhjqcCoL393CvEsoUEj+f+dOaddXrBPjJAulh9MBQQJRJZo/e2eiZLELtPGIYnjG0mCL GavN2t1oIpom+Cw3XbNgK8mqy4VUrzZFtU88hkKgG95IYg/E0krtJec5en2z8SAwmPII i+CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y8d4Rgnl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id b7-20020a170906194700b009b9a53e68basi3388509eje.9.2023.10.07.19.29.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 19:29:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y8d4Rgnl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C1FB03858439 for ; Sun, 8 Oct 2023 02:29:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 37DCD3858C53 for ; Sun, 8 Oct 2023 02:27:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 37DCD3858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696732054; x=1728268054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HaCsJU/DVKvKf/MKwP8fO0AvbXxoGOtv3BmJWwDJrYM=; b=Y8d4Rgnlf8/pTA9UeVqoZ0KgoEF4DCgB3f45l8Rsj2bxjKc5YgxJ3JJI H+/JNmKhI7IF/vxj3T2IbZNnZqE4eLLjiPKP5bGo1CmpjDizAn6optLHM MJJVoNRusKwugjMlALmNZYWhZiLBgu69mj4hI8fhPQYFlnh44CD/jdSYt cFEUvuqSwCxEqjoLc6SjSG20FoFOkEKu7hq+1pY6UJf9GX+9Kqi9NZI9Z f57CzKoKwksDp7nOqCEGM7UiJwYwzYRW9hmz04gt9JmAtaEf4asmYT1Uq XxXGPhpbrUyc8WW2cBuJRQjXBlgp49ZJwdYZfzkVpdkwexCW3yeyszhvH g==; X-IronPort-AV: E=McAfee;i="6600,9927,10856"; a="364262495" X-IronPort-AV: E=Sophos;i="6.03,207,1694761200"; d="scan'208";a="364262495" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2023 19:27:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10856"; a="876427625" X-IronPort-AV: E=Sophos;i="6.03,207,1694761200"; d="scan'208";a="876427625" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 07 Oct 2023 19:27:28 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id E08CB100571A; Sun, 8 Oct 2023 10:27:27 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH 2/2] Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF. Date: Sun, 8 Oct 2023 10:27:27 +0800 Message-Id: <20231008022727.2896829-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231008022727.2896829-1-hongtao.liu@intel.com> References: <20231008022727.2896829-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779152608498740817 X-GMAIL-MSGID: 1779152608498740817 Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Ready push to trunk. gcc/ChangeLog: * config/i386/i386.cc (ix86_build_const_vector): Handle V2HF and V4HFmode. (ix86_build_signbit_mask): Ditto. * config/i386/mmx.md (mmxintvecmode): Ditto. (2): New define_expand. (*mmx_): New define_insn_and_split. (*mmx_nabs2): Ditto. (*mmx_andnot3): New define_insn. (3): Ditto. (copysign3): New define_expand. (xorsign3): Ditto. (signbit2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-absneghf.c: New test. * gcc.target/i386/part-vect-copysignhf.c: New test. * gcc.target/i386/part-vect-xorsignhf.c: New test. --- gcc/config/i386/i386.cc | 4 + gcc/config/i386/mmx.md | 114 +++++++++++++++++- .../gcc.target/i386/part-vect-absneghf.c | 91 ++++++++++++++ .../gcc.target/i386/part-vect-copysignhf.c | 60 +++++++++ .../gcc.target/i386/part-vect-vminmaxph-1.c | 4 +- .../gcc.target/i386/part-vect-xorsignhf.c | 60 +++++++++ 6 files changed, 330 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-absneghf.c create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 9557bffd092..46326d3c82e 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -15752,6 +15752,8 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) case E_V2DImode: gcc_assert (vect); /* FALLTHRU */ + case E_V2HFmode: + case E_V4HFmode: case E_V8HFmode: case E_V16HFmode: case E_V32HFmode: @@ -15793,6 +15795,8 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) switch (mode) { + case E_V2HFmode: + case E_V4HFmode: case E_V8HFmode: case E_V16HFmode: case E_V32HFmode: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 77f1db265ab..c68a3d6fe43 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -99,7 +99,8 @@ (define_mode_attr mmxdoublemode ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr mmxintvecmode - [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")]) + [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI") + (V4HF "V4HF") (V2HF "V2HI")]) (define_mode_attr mmxintvecmodelower [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")]) @@ -2045,6 +2046,117 @@ (define_expand "3" DONE; }) +(define_expand "2" + [(set (match_operand:VHF_32_64 0 "register_operand") + (absneg:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand")))] + "TARGET_SSE" + "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") + +(define_insn_and_split "*mmx_" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x") + (absneg:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x,x"))) + (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (: (match_dup 1) (match_dup 2)))] +{ + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); +} + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_insn_and_split "*mmx_nabs2" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x") + (neg:VHF_32_64 + (abs:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x,x")))) + (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ior: (match_dup 1) (match_dup 2)))]) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Parallel half-precision floating point logical operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn "*mmx_andnot3" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x") + (and:VHF_32_64 + (not:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "0,x")) + (match_operand:VHF_32_64 2 "register_operand" "x,x")))] + "TARGET_SSE" + "@ + andnps\t{%2, %0|%0, %2} + vandnps\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "V4SF")]) + +(define_insn "3" + [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x") + (any_logic:VHF_32_64 + (match_operand:VHF_32_64 1 "register_operand" "%0,x") + (match_operand:VHF_32_64 2 "register_operand" " x,x")))] + "TARGET_SSE" + "@ + ps\t{%2, %0|%0, %2} + vps\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog,sselog") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "V4SF")]) + +(define_expand "copysign3" + [(set (match_dup 4) + (and:VHF_32_64 + (not:VHF_32_64 (match_dup 3)) + (match_operand:VHF_32_64 1 "register_operand"))) + (set (match_dup 5) + (and:VHF_32_64 (match_dup 3) + (match_operand:VHF_32_64 2 "register_operand"))) + (set (match_operand:VHF_32_64 0 "register_operand") + (ior:VHF_32_64 (match_dup 4) (match_dup 5)))] + "TARGET_SSE" +{ + operands[3] = ix86_build_signbit_mask (mode, true, false); + + operands[4] = gen_reg_rtx (mode); + operands[5] = gen_reg_rtx (mode); +}) + +(define_expand "xorsign3" + [(set (match_dup 4) + (and:VHF_32_64 (match_dup 3) + (match_operand:VHF_32_64 2 "register_operand"))) + (set (match_operand:VHF_32_64 0 "register_operand") + (xor:VHF_32_64 (match_dup 4) + (match_operand:VHF_32_64 1 "register_operand")))] + "TARGET_SSE" +{ + operands[3] = ix86_build_signbit_mask (mode, true, false); + + operands[4] = gen_reg_rtx (mode); +}) + +(define_expand "signbit2" + [(set (match_operand: 0 "register_operand") + (lshiftrt: + (subreg: + (match_operand:VHF_32_64 1 "register_operand") 0) + (match_dup 2)))] + "TARGET_SSE2" + "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1);") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral arithmetic diff --git a/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c new file mode 100644 index 00000000000..48aed14d604 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c @@ -0,0 +1,91 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */ + +extern void abort (); + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" + +#define N 16 +_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f, + -12.5f, -15.6f, -18.7f, -21.8f, + 24.9f, 27.1f, 30.2f, 33.3f, + 36.4f, 39.5f, 42.6f, 45.7f}; +_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f, + -9.0f, 1.0f, -2.0f, 3.0f, + -4.0f, -5.0f, 6.0f, 7.0f, + -8.0f, -9.0f, 10.0f, 11.0f}; +_Float16 r[N]; + +void +__attribute__((noipa,noinline,optimize("O2"))) +abs_32 (void) +{ + r[0] = __builtin_fabsf16 (b[0]); + r[1] = __builtin_fabsf16 (b[1]); +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +abs_64 (void) +{ + r[0] = __builtin_fabsf16 (b[0]); + r[1] = __builtin_fabsf16 (b[1]); + r[2] = __builtin_fabsf16 (b[2]); + r[3] = __builtin_fabsf16 (b[3]); +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +neg_32 (void) +{ + r[0] = -b[0]; + r[1] = -b[1]; +} + +void +__attribute__((noipa,noinline,optimize("O2"))) +neg_64 (void) +{ + r[0] = -b[0]; + r[1] = -b[1]; + r[2] = -b[2]; + r[3] = -b[3]; +} + +static void +__attribute__ ((noinline, noclone)) +do_test (void) +{ + abs_32 (); + /* check results: */ + for (int i = 0; i != 2; i++) + if (r[i] != __builtin_fabsf16 (b[i])) + abort (); + + abs_64 (); + /* check results: */ + for (int i = 0; i != 4; i++) + if (r[i] != __builtin_fabsf16 (b[i])) + abort (); + + neg_32 (); + /* check results: */ + for (int i = 0; i != 2; i++) + if (r[i] != -b[i]) + abort (); + + neg_64 (); + /* check results: */ + for (int i = 0; i != 4; i++) + if (r[i] != -b[i]) + abort (); +} + +/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 2 "slp2" } } */ +/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 2 "slp2" } } */ +/* { dg-final { scan-tree-dump-times {(?n)ABS_EXPR